Core Disable Mode; Ipic External Signal Description; Ipic External Signals Overview; Ipic Detailed Signal Descriptions - Freescale Semiconductor MPC8313E Family Reference Manual

In this mode all machine check interrupts are gathered by the IPIC unit and sent to the PowerPC core. If
the device performs as a PCI host, the interrupts of the other PCI agents should be connected to the
implementation's IRQx signals and treated like normal external interrupts (sent to the core).
8.3.2

Core Disable Mode

In core disable mode, all internal interrupts (including those from the PCI block) are routed to and from
the IPIC, the interrupts are then sent through the PCI_INTA signal to the PCI host CPU. Note that the core
interrupt signal is masked. The user should use in this mode only the int output interrupt type (should not
use cint or smi output interrupt types) to read an updated SIVCR. (See
Interrupt Control Register (SICNR),"
(SECNR).")
In this mode, machine check interrupts are driven either on PCI_INTA or on MCP_OUT as level-sensitive
interrupts. SERCR[MCPR] (see
which external signal is used.
8.4

IPIC External Signal Description

The following sections provide an overview and detailed descriptions of the IPIC signals.
8.4.1

IPIC External Signals Overview

The device has 5 distinct external interrupt request input signals (IRQ[0:4]) and one interrupt request
output signal (PCI_INTA). The IPIC interface signals are defined in
Name Port
IRQ[0:4] IRQ[0:4]
PCI_INTA PCI_INTA
MCP_OUT MCP_OUT
8.4.2

IPIC Detailed Signal Descriptions

Table 8-2 provides detailed descriptions of the external IPIC signals.
Table 8-2. IPIC External Signals—Detailed Signal Descriptions
Signal I/O
IRQ[0:4] I Interrupt request 0–4. The sense (level or edge) of each of these signals is programmable. All of these inputs
can be driven completely asynchronously.
State
Meaning
Timing Assertion—All of these inputs can be asserted completely asynchronously.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
and Section 8.5.12, "System External Interrupt Control Register
Section 8.5.15, "System Error Control Register
Table 8-1. IPIC Signal Properties
Function
External interrupts
Interrupt request output
Interrupt request output
Asserted—When an external interrupt request signal is asserted the priority is checked by the IPIC
unit, and the interrupt is conditionally passed to the processor.
Negated—There is no incoming interrupt from that source.
Negation—Interrupts programmed as level-sensitive must remain asserted until serviced.
Integrated Programmable Interrupt Controller (IPIC)
Section 8.5.7, "System Internal
Table 8-1.
Description
(SERCR)") controls
I/O Reset Requires Pull Up
I — Yes
O Z Yes
O Z Yes
8-5