Mdeu Interrupt Control Register (Mdeuicr) - Freescale Semiconductor MPC8313E Family Reference Manual

Security Engine (SEC) 2.2
Bits Name
53 CE Context error. The MDEU key register, key size register, or data size register was modified while MDEU was
hashing.
0 No error detected
1 Context error
54 KSE Key size error. A value greater than 64 bytes was written to the MDEU key size register (MDEUKSR).
0 No error detected
1 Key size error
55 DSE Data size error. A value not a multiple of 512 bits while the MDEU mode register (MDEUMR) CONT bit is high.
0 No error detected
1 Data size error
56 ME Mode error. Will be set if any of these error conditions is detected:
• Any reserved bit of the mode register is set
• The ALG field of the mode register contains an illegal value
0 No error detected
1 Mode error
57 AE Address error. An illegal read or write address was detected within the MDEU address space.
0 No error detected
1 Address error
58–60 — Reserved
61 IFO Input FIFO overflow. The MDEU input FIFO has been pushed while full.
0 No overflow detected
1 Input FIFO has overflowed
Note: When operated through channel-controlled access, the SEC implements flow control, and FIFO size
is not a limit to data input size. When operated through host-controlled access, the MDEU cannot
accept FIFO inputs larger than 256 bytes without overflowing.
62–63 — Reserved
14.4.2.8

MDEU Interrupt Control Register (MDEUICR)

The MDEU interrupt control register (MDEUICR), shown in
errors. For a given error (as defined in
if the corresponding bit in this register is set, then the error is disabled; no error interrupt occurs and the
MDEU interrupt status register (MDEUISR) is not updated to reflect the error. If the corresponding bit is
not set, then upon detection of an error, the interrupt status register is updated to reflect the error, causing
assertion of the error interrupt signal, and causing the module to halt processing.
0
Field
Reset
R/W
Addr
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
14-36
Table 14-23. MDEUISR Field Descriptions (continued)
Section 14.4.2.7, "MDEU Interrupt Status Register
48 49
— ICE —
Figure 14-22. MDEU Interrupt Control Register (MDEUICR)
Description
Figure 14-22, controls the result of detected
50 51 52 53 54
IE ERE CE KSE DSE ME AE
0x3000
R/W
MDEU 0x3_6038
(MDEUISR)"),
55 56 57 58 60 61
— IFO
Freescale Semiconductor
62 63
—