Fifo Control Registers (Ufcr1 And Ufcr) - Freescale Semiconductor MPC8313E Family Reference Manual

Powerquicc ii pro integrated processor
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DUART
Table 18-10
describes the fields of the UIIR.
Bits
Name
0–1
FE
FIFOs enabled. Reflects the setting of UFCR[FEN].
2–3
Reserved
4
IID3
Interrupt ID bits identify the highest priority interrupt that is pending as indicated in
along with IID2 only when a time out interrupt is pending for FIFO mode.
5–6
IID2–IID1 Interrupt ID bits identify the highest priority pending interrupt as indicated in
7
IID0
IID0 indicates when an interrupt is pending.
0 The UART has an active interrupt ready to be serviced.
1 No interrupt is pending.
The bits contained in the UIIR registers are described in
IID3–
Priority
Interrupt Type
IID0
Level
0001
0110
Highest
Receiver line status
0100
Second
Received data available Receiver data available or trigger level
1100
Second
Character time-out
0010
Third
0000
Fourth
MODEM status
18.3.1.6
FIFO Control Registers (UFCR1 and UFCR2)
UFCR is used to enable and clear the receiver and transmitter FIFOs, set a receiver FIFO trigger level to
control the received data available interrupt, and select the type of DMA signaling.
UFCR bits cannot be programmed unless FIFO enable bits are set. When changing from FIFO mode to
16450 mode (non-FIFO mode) and vice versa, data is automatically cleared from the FIFOs.
After all of the bytes in the receiver FIFO are cleared, the receiver internal shift register is not cleared.
Similarly, the bytes are cleared in the transmitter FIFO, but the transmitter internal shift register is not
cleared. Both TFR and RFR are self clearing.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
18-10
Table 18-10. UIIR Field Descriptions
Table 18-11. UIIR IID Bits Summary
Overrun error, parity error, framing error, or
break interrupt
reached in FIFO mode.
No characters were removed from or input to
the receiver FIFO during the last four
character times and at least one character is
in the receiver FIFO.
UTHR empty
Transmitter holding register is empty.
CTS input value changed since last read of
UMSR.
Description
Table
18-11.
Interrupt Description
Table
18-11. IID3 is set
Table
18-11.
How To Reset Interrupt
Reading the line status register
Reading the receiver buffer
register or if the number of
bytes in the receiver FIFO
drops below the trigger level.
Reading the receiver buffer
register
Reading UIIR or writing to
UTHR
Reading UMSR
Freescale Semiconductor

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