Embedded Transaction Translator Function - Freescale Semiconductor MPC8313E Family Reference Manual

• Device operation—In host mode, the device operational registers are generally disabled and thus
device mode is mostly transparent when in host mode. However, there are a couple exceptions
documented in the following sections.
• Embedded design interface—The module does not have a PCI interface and therefore the PCI
configuration registers described in the EHCI specification are not applicable.
• For the purposes of the DR implementing dual-role host/device controller with support for OTG
applications, it is necessary to deviate from the EHCI specification. Device operation and OTG
operation are not specified in the EHCI and thus the implementation supported in the DR module
is proprietary.
16.9.1

Embedded Transaction Translator Function

The DR module supports directly connected full and low speed devices without requiring a companion
controller by including the capabilities of a USB 2.0 high speed hub transaction translator. Although there
is no separate transaction translator block in the system, the transaction translator function normally
associated with a high speed hub has been implemented within the DMA and Protocol engine blocks. The
embedded transaction translator function is an extension to EHCI interface, but makes use of the standard
data structures and operational models that exist in the EHCI specification to support full and low speed
devices.
16.9.1.1 Capability Registers
The following additions have been added to the capability registers to support the embedded transaction
translator Function:
• N_TT added to HSCPARAMS—Host Controller Structural Parameters
• N_PTT added to HSCPARAMS—Host Controller Structural Parameters
See Section 16.3.1.3, "Host Controller Structural Parameters (HCSPARAMS),"
16.9.1.2 Operational Registers
The following additions have been added to the operational registers to support the embedded TT:
• ASYNCTTSTS is a new register.
• Addition of two-bit Port Speed (PSPD) to the PORTSC register.
16.9.1.3 Discovery
In a standard EHCI controller design, the EHCI host controller driver detects a Full speed (FS) or Low
speed (LS) device by noting if the port enable bit is set after the port reset operation. The port enable will
only be set in a standard EHCI controller implementation after the port reset operation and when the host
and device negotiate a High-Speed connection (that is, Chirp completes successfully).
The module always sets the port enable after the port reset operation regardless of the result of the host
device chirp result. The resulting port speed is indicated by the PSPD field in PORTSC. Therefore, the
standard EHCI host controller driver requires an alteration to handle directly connected full- and
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Universal Serial Bus Interface
for usage information.
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