Connecting To Physical Interfaces On Ethernet - Freescale Semiconductor MPC8313E Family Reference Manual

Bits Name
11 MI Mode This bit describes the configuration mode of the TBI. The user reads a 1 while the TBI is configured in
GMII/MII mode (connected to a GMII/MII PHY) and a 0 while configured in TBI mode (connected to a
1000BASE-X SerDes). Its value is the inverse of ECNTRL[TBIM].
0 TBI mode.
1 GMII mode.
12–15 — Reserved
15.6 Functional Description
15.6.1

Connecting to Physical Interfaces on Ethernet

This section describes how to connect the eTSEC to various interfaces: MII, RMII, RGMII, and RTBI. To
avoid confusion, all of the buses follow the bus conventions used in the IEEE 802.3 specification because
the PHYs follow the same conventions. (For instance, in the bus TSECn_TXD[3:0], bit 3 is the msb and
bit 0 is the lsb). If a mode does not use all input signals available to a particular eTSEC, those inputs that
are not used must be pulled low on the board.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Table 15-136. TBICON Field Descriptions (continued)
Enhanced Three-Speed Ethernet Controllers
Description
15-135