Freescale Semiconductor MPC8313E Family Reference Manual page 155

Table 3-1. MPC8313E Signal Reference by Functional Block (continued)
Name
LSRCID4 Memory debug
source ID 4
LDVAL Memory debug data
valid
1
The LB_POR_CFG_BOOT_ECC_DIS function will be selected on the TSEC_MDC pin whenever HRESET is asserted; the pin
will act as TSEC_MDC at all other times. The reset block will sample this signal on PORESET negation only; the sampled value
is then passed to the eLBC controller to enable/disable ECC checking during boot time.
2
See Table 3-3 for proper connection to power.
3
See H/W specification for resistor values.
4
Must be connected to a 10K ±1% precision resistor if using the integrated USB PHY through the UTMI.
Table 3-2 lists the signals in alphabetical order.
Name
CFG_CLKIN_DIV Configuration clock
in division selection
CFG_LBIU_MUX_EN Selects multiplexing
for address/data bus
of the eLBC block
CKSTOP_IN Clock stop in
CKSTOP_IN Clock stop in
CKSTOP_OUT Clock stop out
CKSTOP_OUT Clock stop out
CPCI_HS_ENUM CompactPCI hot
swap enumerator
CPCI_HS_ES CompactPCI hot
swap ejector switch
CPCI_HS_LED CompactPCI hot
swap LED
EXT_PWR_CTRL External power
control
GPIO[0:4] General-purpose
I/O signals 0-4
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Functional
Description
Block
Debug
Debug
Table 3-2. MPC8313E Signal Reference by Signal Name
Functional
Description
Block
Reset and
clock
Reset and
clock
Reset and
clock
Reset and
clock
Reset and
clock
Reset and
clock
PCI
PCI
PCI
PMC
GPIO
No. of Table/
I/O
Signals Page
1 I/O 10-2/10-5
1 I/O 10-2/10-5
No. of Table/
I/O
Signals Page
1 I 3-3/3-29
1 I 3-6/3-32
1 I/O —
1 I/O —
1 I/O —
1 I/O —
1 O 13-3/13-5
1 I 13-3/13-5
1 O 13-3/13-5
1 O 5-64/5-67
5 I/O 21-1/21-2
Signal Descriptions
Alternate Table/
Function(s) Page
GTM1_TIN3/ 5-27/5-21,
GTM2_TIN4/ 21-1/21-2,
GPIO[28]/SPIMOSI 19-2/19-7
GTM1_TGATE3/ 5-27/5-21,
GTM2_TGATE4/ 21-1/21-2,
GPIO[29]/SPIMISO 19-2/19-7
Alternate Table/
Function(s) Page
—
—
IIC1_SCL 17-1/17-3
GPIO[12]/ IRQ[4] 21-1/21-2,
8-2/8-5
IIC1_SDA 17-1/17-3
IRQ[3] 8-2/8-5
PCI_GNT2 13-3/13-5
PCI_REQ1 13-3/13-5
PCI_GNT1 13-3/13-5
—
LA[0:4]/MSRCID[0:4] 10-2/10-5,
9-1/9-3
—
—
—
3-17