Freescale Semiconductor MPC8313E Family Reference Manual page 969

force signaling and allows software to put the PHY into low power suspend mode and disable the PHY
clock.
Offset 0x184
31 30 29 28
R
PTS — —
W
Reset 0 0 0
15 14 13 12
R
PIC PO PP
W
Reset 0 0 0
Table 16-23 describes the PORTSC register fields.
Bits Name
31–30 PTS Port transceiver select. This register bit is used to control which parallel transceiver interface is selected.
00 UTMI parallel interface
01 Reserved, should be cleared
10 ULPI parallel interface
11 Reserved
This bit is not defined in the EHCI specification.
29 — Reserved, should be cleared
28 — Reserved
27–26 PSPD Port speed. This read-only register field indicates the speed at which the port is operating.
This bit is not defined in the EHCI specification.
00 Full-speed
01 Low-speed
10 High-speed
11 Undefined
25 — Reserved, should be cleared
24 PFSC Port force full-speed connect. Used to disable the chirp sequence that allows the port to identify itself as a HS
port. This is useful for testing FS configurations with a HS host, hub or device.
0 Allow the port to identify itself as high speed.
1 Force the port to only connect at full speed.
This bit is not defined in the EHCI specification.
This bit is for debugging purposes.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
27 26 25
PSPD
—
1 0 0 0
11 10 9
LS
—
0 0 0 0
Figure 16-20. Port Status and Control (PORTSC)
Table 16-23. PORTSC Register Field Descriptions
24 23 22
PFSC PHCD WKOC WKDS WKCN
0 0 0
8 7 6
OCC
PR SUSP FPR
w1c
0 0 0
Description
Universal Serial Bus Interface
21 20 19
0 0 0 0
5 4 3 2
OCA PEC
PE
w1c
0 0 0 0
Access: Mixed
16
PTC
0 0
1 0
CSC CCS
w1c
0 0
16-27