Freescale Semiconductor MPC8313E Family Reference Manual page 7

Paragraph
Number
5.3.2.5 System I/O Configuration Register Low (SICRL) ................................................ 5-21
5.3.2.6 System I/O Configuration Register High (SICRH) ............................................... 5-23
5.3.2.7 Debug Configuration ............................................................................................. 5-26
5.3.2.7.1
5.3.2.7.2
5.3.2.8 DDR Control Driver Register (DDRCDR)............................................................ 5-27
5.3.2.9 DDR Debug Status Register (DDRDSR) .............................................................. 5-28
5.4 Software Watchdog Timer (WDT)................................................................................. 5-29
5.4.1 WDT Overview.......................................................................................................... 5-29
5.4.2 WDT Features............................................................................................................ 5-30
5.4.3 WDT Modes of Operation ......................................................................................... 5-30
5.4.4 WDT Memory Map/Register Definition ................................................................... 5-31
5.4.4.1 System Watchdog Control Register (SWCRR) ..................................................... 5-31
5.4.4.2 System Watchdog Count Register (SWCNR) ....................................................... 5-32
5.4.4.3 System Watchdog Service Register (SWSRR)...................................................... 5-33
5.4.5 Functional Description............................................................................................... 5-34
5.4.5.1 Software Watchdog Timer Unit ............................................................................. 5-34
5.4.5.2 Modes of Operation ............................................................................................... 5-35
5.4.6 Initialization/Application Information ....................................................................... 5-36
5.4.6.1 WDT Programming Guidelines............................................................................. 5-36
5.5 Real Time Clock Module (RTC).................................................................................... 5-36
5.5.1 RTC Overview ........................................................................................................... 5-36
5.5.2 RTC Features ............................................................................................................. 5-37
5.5.3 RTC Modes of Operation........................................................................................... 5-37
5.5.4 RTC External Signal Description .............................................................................. 5-37
5.5.5 RTC Memory Map/Register Definition ..................................................................... 5-38
5.5.5.1 Real Time Counter Control Register (RTCNR) .................................................... 5-38
5.5.5.2 Real Time Counter Load Register (RTLDR)......................................................... 5-39
5.5.5.3 Real Time Counter Prescale Register (RTPSR) .................................................... 5-40
5.5.5.4 Real Time Counter Register (RTCTR) .................................................................. 5-40
5.5.5.5 Real Time Counter Event Register (RTEVR)........................................................ 5-41
5.5.5.6 Real Time Counter Alarm Register (RTALR) ....................................................... 5-41
5.5.6 Functional Description............................................................................................... 5-42
5.5.6.1 Real Time Counter Unit......................................................................................... 5-42
5.5.6.2 RTC Operational Modes ........................................................................................ 5-42
5.5.7 RTC Programming Guidelines................................................................................... 5-43
5.6 Periodic Interval Timer (PIT) ........................................................................................ 5-43
5.6.1 PIT Overview............................................................................................................. 5-44
5.6.2 PIT Features............................................................................................................... 5-44
5.6.3 PIT Modes of Operation ............................................................................................ 5-44
5.6.4 PIT External Signal Description ................................................................................ 5-45
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Contents
DDR Debug Configuration................................................................................ 5-27
Local Bus Debug Configuration........................................................................ 5-27
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Page
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vii