Real Time Counter Event Register (Rtevr); Real Time Counter Alarm Register (Rtalr) - Freescale Semiconductor MPC8313E Family Reference Manual

5.5.5.5

Real Time Counter Event Register (RTEVR)

The real time counter event register (RTEVR), shown in
interrupts. The register can be read at any time.
Offset 0x10
0
R
W
Reset
RTEVR bits are cleared by writing ones. Writing zeros does not affect the value of the status bits.
Table 5-43 defines the bit fields of RTEVR.
Bits Name
0–29 — Write reserved, read = 0
30 AIF Alarm interrupt flag bit.
Used to indicate the alarm interrupt. The bit is set if the RTC issues an interrupt when the RTC counter value
equals RTALR[ALRM].
31 SIF Second interrupt flag bit.
Used to indicate the every-second interrupt. This status bit is set each time that the prescaler count reaches
zero and should be cleared by software.
5.5.5.6

Real Time Counter Alarm Register (RTALR)

The real time counter alarm register (RTALR), shown in
value. When the value of the RTC counter equals the RTALR[ALRM] value, a maskable interrupt is
generated.
Offset 0x14
0
R
W
Reset 1 1 1 1 1
Table 5-44 defines the bit fields of RTALR.
Bits Name
0–31 ALRM RTC alarm value.
The alarm interrupt is generated when the value of the RTC counter equals RTALR[ALRM].
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Figure 5-29. Real Time Counter Event Register (RTEVR)
Table 5-43. RTEVR Bit Settings
1 1 1 1 1 1 1 1
Figure 5-30. Real Time Counter Alarm Register (RTALR)
Table 5-44. RTALR Bit Settings
Figure 5-29, is used to report the source of the
—
All zeros
Description
Figure 5-30, contains the 32-bit alarm (ALRM)
ALRM
1 1 1 1 1 1 1 1
Description
System Configuration
Access: w1c
Access: Read/Write
1 1 1 1 1 1 1 1
29 30 31
AIF SIF
w1c w1c
31
1 1 1
5-41