Paragraph
Number
15.5.3.3.4
15.5.3.3.5
15.5.3.3.6
15.5.3.3.7
15.5.3.3.8
15.5.3.3.9
15.5.3.3.10
15.5.3.3.11
15.5.3.3.12
15.5.3.3.13
15.5.3.4
15.5.3.4.1
15.5.3.4.2
15.5.3.4.3
15.5.3.4.4
15.5.3.4.5
15.5.3.5
15.5.3.5.1
15.5.3.5.2
15.5.3.5.3
15.5.3.5.4
15.5.3.5.5
15.5.3.5.6
15.5.3.5.7
15.5.3.5.8
15.5.3.5.9
15.5.3.5.10
15.5.3.5.11
15.5.3.5.12
15.5.3.5.13
15.5.3.5.14
15.5.3.5.15
15.5.3.5.16
15.5.3.6
15.5.3.6.1
15.5.3.6.2
15.5.3.6.3
15.5.3.6.4
15.5.3.6.5
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
xxiv
Contents
Receive Queue Filer Table Address Register (RQFAR) ................................. 15-56
Receive Buffer Descriptor Pointers 0-7 (RBPTR0-RBPTR7) ....................... 15-62
Receive Descriptor Base Address Registers (RBASE0-RBASE7) ................ 15-63
MAC Configuration 1 Register (MACCFG1)................................................. 15-67
MAC Configuration 2 Register (MACCFG2)................................................. 15-68
MAC Station Address Part 1 Register (MACSTNADDR1) ........................... 15-77
MAC Station Address Part 2 Register (MACSTNADDR2) ........................... 15-78
(MAC01ADDR1-MAC15ADDR1)............................................................ 15-78
(MAC01ADDR2-MAC15ADDR2)............................................................ 15-79
Transmit and Receive 64-Byte Frame Counter (TR64) .................................. 15-80
Transmit and Receive 65- to 127-Byte Frame Counter (TR127) .................... 15-81
Transmit and Receive 128- to 255-Byte Frame Counter (TR255) .................. 15-81
Transmit and Receive 256- to 511-Byte Frame Counter (TR511) .................. 15-82
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Page
Number
Freescale Semiconductor