Reset Configuration Words - Freescale Semiconductor MPC8313E Family Reference Manual

Powerquicc ii pro integrated processor
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Reset, Clocking, and Initialization
Table 4-7. Selecting Reset Configuration Input Signals (continued)
2
I
C EEPROM
SYS_CLK_IN
Configuration
Frequency
Words
(Host Mode)
No
66 MHz
Yes
33 MHz
Yes
66 MHz
Yes
66 MHz
No
66 MHz
No
66 MHz
4.3.2

Reset Configuration Words

The reset configuration words control the clock ratios and other basic device functions such as PCI host
or agent mode, boot location, and endian mode. The reset configuration words are loaded from NOR Flash,
2
NAND Flash, or the I
C interfaces or from hard-coded values during the power-on or hard reset flows. See
Section 4.3.1, "Reset Configuration Signals,"
Although the configuration reset words are loaded during hard reset flows, the clocks and PLL modes are
reset only when PORESET is asserted during a power-on reset flow. See
The values of fields in the reset configuration words registers (RCWLR and RCWHR) reflect only their
state during the reset flow. Some of these parameters and modes can be modified by changing their values
in the memory-mapped registers of other units, which does not affect RCWLR and RCWHR.
The reset configuration settings are accessible to software through the following read-only
memory-mapped registers:
Reset configuration word low register (RCWLR)
Reset configuration word high register (RCWHR)
Reset status register (RSR)
System PLL mode register (SPMR)
See
Section 4.5, "Memory Map/Register Definitions."
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
4-12
PCI_CLK
CFG_CLKIN_DIV
Frequency
(Host Mode)
(Agent Mode)
0
33 MHz
1
33 MHz
1
66 MHz
0
33 MHz
1
66 MHz
1
66 MHz
for information on the reset configuration word source.
CFG_RESET_
SOURCE[0:3]
0000
(RCW loaded from NOR
Flash)
2
0100 (I
C EEPROM)
2
0100 (I
C EEPROM)
2
0100 (I
C EEPROM)
0001 (RCW loaded from
8-bit small page NAND
Flash)
0101 (RCW loaded from
8-bit large page NAND
Flash)
Section 4.2.1.2, "Reset Actions."
Reset Sequence
Duration in
SYS_CLK_IN/
Duration
PCI_CLK
Cycles
μ
30420/15210
456
s
μ
106534
3196
μ
106534
1598
μ
213068/106534
3196
μ
23024
345
s
μ
45284
679
s
Freescale Semiconductor
s
s
s

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