Pci Command Configuration Register - Freescale Semiconductor MPC8313E Family Reference Manual

PCI Bus Interface
13.3.3.3

PCI Command Configuration Register

Figure 13-21 shows the PCI command fields.
Offset 04
15
R
—
W
Reset
Table 13-25 shows the bit settings of the PCI command register.
Table 13-25. PCI Command Configuration Register Field Descriptions
Bits Name
15–11 —
10 INTD
9 FB-B
8 SERREN
7 —
6 PERRR
5 —
4 MWI
3 SC
2 BMST
1 MEM
0 I/O
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
13-28
11 10 9
FB-B
INTD
Figure 13-21. PCI Command Configuration Register
Reserved
Interrupt Disable. Setting this bit masks the PCI_INTA output.
0 PCI_INTA provides the device interrupt status.
1 PCI_INTA is always negated.
Fast back-to-back. Hard-wired to 0.
SERR enable. This bit is an enable bit for the SERR driver. Address parity errors are reported only
if this bit and bit 6 are 1.
0 PCI_SERR is never asserted.
1 PCI_SERR may be asserted to indicate error conditions.
Reserved
Parity error response. Controls the PCI controller's response to a parity error.
0 Parity errors are ignored and normal operation continues.
1 Standard parity error treatment.
Reserved
Memory-write-and-invalidate. Hard-wired to 0.
Special cycles. Hard-wired to 0.
Bus master. Controls the PCI controller's ability to be a master on the PCI bus. At reset, this bit is
cleared in Agent Mode and set in Host Mode.
0 The PCI controller does not generate PCI accesses.
1 The PCI controller behaves as a bus master.
Memory space. Controls the response to memory space accesses.
0 The PCI controller does not respond to Memory Space accesses.
1 The PCI controller as a target responds to Memory Space accesses.
I/O space. Hard-wired to 0.
8 7 6
SERREN — PERRR
All zeros
Description
Access: Mixed
5 4 3 2
MWI SC
— BMST MEM
Freescale Semiconductor
1 0
I/O