Freescale Semiconductor MPC8313E Family Reference Manual page 282

System Configuration
Table 5-69 defines the bit fields of PMCCR1.
Bits Name
0 USE_STATE
1–22 —
23 LLPEN
24 PME_EN
25 ASSERT_PME Normally PCI_PME output is asserted automatically by PMC when a defined wake-up event occurs
26 POWER_OFF
27 —
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
5-72
Table 5-69. PMCCR1 Bit Settings
Controls whether the next and current state values should be used. This typically depends on the
device operating mode (PCI host or agent).
0 Ignore the next and current state values (host mode).
1 Use the next and current state values (agent mode). When next state does not equal current
state, an interrupt will be sent to the e300 CPU.
Reserved, must be cleared.
SerDes low power enable bit. This bit dictates whether the SerDes is intended to be switched off or
not when the chip goes into low power mode.
0 SerDes will be switched off when the chip goes into low power mode.
1 SerDes will not be switched off when the chip goes into low power mode. (This would be needed
when wake-up through SGMII is intended.)
PME (power management event) signaling enable. Clearing this bit typically indicates the device is
acting as PCI host, meaning that PCI_PME is a wake-up input to device. Setting this bit typically
indicates that the device is a PCI agent and will assert PCI_PME on wake-up. PME_EN does not
qualify the assertion of PCI_PME when setting the PMCCR1[ASSERT_PME] bit to 1.
0 Mask PME signaling when wake-up events occur.
1 Allow PME signaling when wake-up events occur.
assuming PMCCR1[PME_EN] = 1 and PCIPMCR1[PME_EN] = 1. A defined wake-up event refers
to those events that are registered in bits 23–30 of PMCER. ASSERT_PME allows PCI_PME to be
asserted manually, by the e300. This would be done to inform the host of a power state change
when PMC does not generate PCI_PME automatically, for example waking from D1 due to CSB bus
activity. ASSERT_PME is not qualified by PMCCR1[PME_EN]. ASSERT_PME is cleared when the
PCI_PME signal is asserted.
0 PCI_PME will only be asserted automatically when a defined wake-up event occurs.
1 Assert the PCI_PME signal under software control (manually).
Distinguishes between D3Hot and D3Warm. If this bit is set, EXT_PWR_CTRL will be toggled in D3
causing VDD to be switched off (if implemented externally).
0 Do not use D3warm state. Always assert the EXT_PWR_CTRL output.
1 On transitions to D3 state, negate the EXT_PWR_CTRL signal to switch external power low
(VDD = 0). On wake-up assert EXT_PWR_CTRL to switch VDD power on.
Reserved
Description
Freescale Semiconductor