Freescale Semiconductor MPC8313E Family Reference Manual page 616

PCI Bus Interface
13.3.2.13 PCI Inbound Extended Base Address Registers (PIEBAR n )
PIEBARn contains fields for defining the high portion of the starting point of the inbound windows in the
PCI memory space. Figure 13-17
Offset 0x44 (n=2)
0x5C (n=1)
0
R
W
Reset
Figure 13-17. PCI Inbound Extended Base Address Registers (PIEBAR n )
Table 13-20 shows the bit settings of PIEBARn.
Bits Name
0–11 —
12–31 EBA
13.3.2.14 PCI Inbound Window Attribute Registers (PIWAR n )
PIWARn contains fields for defining the size of an inbound translation window. It also defines some
properties of the window.
Configuration Word Source,"
Offset 0x48 (n=2)
0x60 (n=1)
0x78 (n=0)
0 1 2 3
R
EN — PF
W
Reset
Figure 13-18. PCI Inbound Window Attribute Registers (PIWAR n )
Table 13-21 shows the bit settings of PIWARn.
Bits Name
0 EN
1 —
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
13-24
shows the PIEBARn fields.
11 12
—
Table 13-20. PIEBAR n Field Descriptions
Reserved
Extended base address. Contains the high portion of the starting address in the PCI memory space
of the inbound base address. This 20-bit field corresponds to bits 63–44 of a 64-bit address.
Figure 13-18 shows the PIWARn fields.
for more information on reset configuration.
11 12
—
Table 13-21. PIWAR n Field Descriptions
Enable. Used to enable the address translation window.
0 Address translation is disabled for this window.
1 Address translation is enabled for this window. PCI addresses that match the definition of the
window will be recognized by the PCI controller and translated to the local memory space.
Reserved
EBA
All zeros
Description
SeeSection 4.3.1.1, "Reset
15 16 19 20
RTT WTT
All zeros
Description
Access: Read/Write
Access: Read/Write
25 26
— IWS
Freescale Semiconductor
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31