Freescale Semiconductor MPC8313E Family Reference Manual page 69

Table
Number
15-127 SR Descriptions................................................................................................................. 15-126
15-128 ANA Field Descriptions.................................................................................................... 15-127
15-129 PAUSE Priority Resolution............................................................................................... 15-128
15-130 ANLPBPA Field Descriptions .......................................................................................... 15-129
15-131 ANEX Field Descriptions ................................................................................................. 15-130
15-132 ANNPT Field Descriptions ............................................................................................... 15-131
15-133 ANLPANP Field Descriptions .......................................................................................... 15-132
15-134 EXST Field Descriptions .................................................................................................. 15-133
15-135 JD Field Descriptions........................................................................................................ 15-134
15-136 TBICON Field Descriptions ............................................................................................. 15-135
15-137 MII and RMII Signals Multiplexing ................................................................................. 15-140
15-138 RGMII and RTBI Signals Multiplexing............................................................................ 15-140
15-139 RGMII Signals Multiplexing ............................................................................................ 15-141
15-140 Shared Signals................................................................................................................... 15-142
15-141 Steps for Minimum Register Initialization........................................................................ 15-143
15-142 Custom Preamble Field Descriptions................................................................................ 15-148
15-143 Received Preamble Field Descriptions ............................................................................. 15-149
15-144 Flow Control Frame Structure .......................................................................................... 15-153
15-145 Non-Error Transmit Interrupts .......................................................................................... 15-155
15-146 Non-Error Receive Interrupts............................................................................................ 15-155
15-147 Interrupt Coalescing Timing Threshold Ranges ............................................................... 15-156
15-148 Transmission Errors .......................................................................................................... 15-157
15-149 Reception Errors ............................................................................................................... 15-158
15-150 Tx Frame Control Block Descriptions .............................................................................. 15-161
15-151 Rx Frame Control Block Descriptions.............................................................................. 15-163
15-152 Special Filer Rules ............................................................................................................ 15-167
15-153 Receive Queue Filer Interrupt Events ............................................................................... 15-167
15-154 Filer Table Example—802.1p Priority Filing ................................................................... 15-168
15-155 Filer Table Example—IP Diff-Serv Code Points Filing ................................................... 15-169
15-156 Filer Table Example—TCP and UDP Port Filing............................................................. 15-170
15-157 PTP Payload Special Fields............................................................................................... 15-177
15-158 Transmit Data Buffer Descriptor (TxBD) Field Descriptions .......................................... 15-181
15-159 Receive Buffer Descriptor Field Descriptions .................................................................. 15-184
15-160 MII Interface Mode Signal Configuration ........................................................................ 15-186
15-161 Shared MII Signals............................................................................................................ 15-187
15-162 MII Mode Register Initialization Steps............................................................................. 15-187
15-163 RGMII Interface Mode Signal Configuration................................................................... 15-189
15-164 Shared RGMII Signals ...................................................................................................... 15-190
15-165 RGMII Mode Register Initialization Steps ....................................................................... 15-190
15-166 RMII Interface Mode Signal Configuration...................................................................... 15-193
15-167 Shared RMII Signals ......................................................................................................... 15-193
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
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