Freescale Semiconductor MPC8313E Family Reference Manual page 54

Figure
Number
2
17-2 I Cn Address Register (I2CnADR)....................................................................................... 17-5
2
17-3 I Cn Frequency Divider Register (I2CnFDR) ...................................................................... 17-6
2
17-4 I Cn Control Register (I2CnCR)........................................................................................... 17-7
2
17-5 I Cn Status Register (I2CnSR) ............................................................................................. 17-8
2
17-6 I Cn Data Register (I2CnDR) ............................................................................................... 17-9
2
17-7 I Cn Digital Filter Sampling Rate Register (I2CnDFSRR) .................................................. 17-9
2
17-8 I C Interface Transaction Protocol...................................................................................... 17-10
17-9 EEPROM Contents ............................................................................................................. 17-17
17-10 EEPROM Data Format for One Register Preload Command............................................. 17-18
2
17-11 Example I C Interrupt Service Routine Flowchart ............................................................. 17-20
18-1 UART Block Diagram .......................................................................................................... 18-2
18-2 Receiver Buffer Registers (URBR1 and URBR2) ................................................................ 18-6
18-3 Transmitter Holding Registers (UTHR1 and UTHR2) ......................................................... 18-6
18-4 Divisor Most Significant Byte Registers (UDMB1 and UDMB2) ....................................... 18-7
18-5 Divisor Least Significant Byte Registers (UDLB1 and UDLB2)......................................... 18-7
18-6 Interrupt Enable Registers (UIER1 and UIER2)................................................................... 18-8
18-7 Interrupt ID Registers (UIIR1 and UIIR2)............................................................................ 18-9
18-8 FIFO Control Registers (UFCR1 and UFCR2)................................................................... 18-11
18-9 Alternate Function Register (UAFR) .................................................................................. 18-11
18-10 Line Control Register (ULCR1 and ULCR2) ..................................................................... 18-12
18-11 Modem Control Register (UMCR1 and UMCR2).............................................................. 18-14
18-12 Line Status Register (ULSR1 and ULSR2) ........................................................................ 18-14
18-13 Modem Status Register (UMSR1 and UMSR2) ................................................................. 18-16
18-14 Scratch Register (USCR) .................................................................................................... 18-16
18-15 DMA Status Register (UDSR) ............................................................................................ 18-17
18-16 UART Bus Interface Transaction Protocol Example .......................................................... 18-19
19-1 SPI Block Diagram ............................................................................................................... 19-2
19-2 Single-Master/Multi-Slave Configuration ............................................................................ 19-4
19-3 Multiple-Master Configuration ............................................................................................. 19-6
19-4 SPMODE-SPI Mode Register Definition ............................................................................. 19-9
19-5 SPI Transfer Format with SPMODE[CP] = 0..................................................................... 19-11
19-6 SPI Transfer Format with SPMODE[CP] = 1..................................................................... 19-11
19-7 SPIE—SPI Event Register Definition................................................................................. 19-12
19-8 SPIM—SPI Mask Register Definition................................................................................ 19-13
19-9 SPI Command Register Definition ..................................................................................... 19-14
19-10 SPI Transmit Data Hold Register Definition ...................................................................... 19-14
19-11 SPI Receive Data Hold Register Definition........................................................................ 19-15
19-12 Example SPMODE[REV] = 0 SPMODE[LEN] = 7 LSB Sent First.................................. 19-15
19-13 Example SPMODE[REV] = 1 SPMODE[LEN] = 7 MSB Sent First................................. 19-15
19-14 Example SPMODE[REV] = 1 SPMODE[LEN] = 15 MSB Sent First............................... 19-16
19-15 Example SPMODE[REV] = 0 SPMODE[LEN] = 15 LSB Sent First................................ 19-16
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
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Freescale Semiconductor