Freescale Semiconductor MPC8313E Family Reference Manual page 539

Powerquicc ii pro integrated processor

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signal of the corresponding bank depends on the value of each CSTn bit.

control LCSn signals.

Byte Select Signal Timing (BST n )

If BRn[MSEL] of the accessed memory bank selects a UPM on the currently requested cycle, the selected

UPM affects the assertion and negation of the appropriate LBS[0:1] signal. The timing of both byte-select

signals is specified in the RAM word. However, LBS[0:1] are also controlled by the port size of the

MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3

Freescale Semiconductor

Bank Selected

Bank Selected

Figure 10-65. LCS n Signal Selection

Enhanced Local Bus Controller

Figure 10-65

shows how UPMs

Chapters

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