Asynchronous Schedule - Freescale Semiconductor MPC8313E Family Reference Manual

state (current microframe, plus the next) on chip. On each microframe boundary, the host controller
releases the current microframe state and begins accumulating the next microframe state.
16.6.9

Asynchronous Schedule

The asynchronous schedule traversal is enabled or disabled through USBCMD[ASE] (asynchronous
schedule enable). If USBCMD[ASE] is cleared, then the host controller simply does not try to access the
asynchronous schedule via the ASYNCLISTADDR register. Likewise, if USBCMD[ASE] is set, the host
controller does use the ASYNCLISTADDR register to traverse the asynchronous schedule. Modifications
to USBCMD[ASE] are not necessarily immediate. Rather the new value of the bit will only be taken into
consideration the next time the host controller needs to use the value of the ASYNCLISTADDR register
to get the next queue head.
USBSTS[AS] indicates status of the asynchronous schedule. System software enables (or disables) the
asynchronous schedule by writing a one (or zero) to USBCMD[ASE]. Software then can poll
USBSTS[AS] to determine when the asynchronous schedule has made the desired transition. Software
must not modify USBCMD[ASE] unless the value of USBCMD[ASE] equals that of the USBSTS[AS]
(asynchronous schedule status).
The asynchronous schedule is used to manage all Control and Bulk transfers. Control and Bulk transfers
are managed using queue head data structures. The asynchronous schedule is based at the
ASYNCLISTADDR register. The default value of the ASYNCLISTADDR register after reset is undefined
and the schedule is disabled when USBCMD[ASE] is cleared.
Software may only write this register with defined results when the schedule is disabled, for example,
USBCMD[ASE] and the USBSTS[AS] are cleared. System software enables execution from the
asynchronous schedule by writing a valid memory address (of a queue head) into this register. Then
software enables the asynchronous schedule by setting USBCMD[ASE]. The asynchronous schedule is
actually enabled when USBSTS[AS] is set.
When the host controller begins servicing the asynchronous schedule, it begins by using the value of the
ASYNCLISTADDR register. It reads the first referenced data structure and begins executing transactions
and traversing the linked list as appropriate. When the host controller completes processing the
asynchronous schedule, it retains the value of the last accessed queue head's horizontal pointer in the
ASYNCLISTADDR register. Next time the asynchronous schedule is accessed, this is the first data
structure that is serviced. This provides round-robin fairness for processing the asynchronous schedule.
A host controller completes processing the asynchronous schedule when one of the following events
occur:
• The end of a microframe occurs.
• The host controller detects an empty list condition
• The schedule has been disabled through USBCMD[ASE].
The queue heads in the asynchronous list are linked into a simple circular list as shown in
Queue head data structures are the only valid data structures that may be linked into the asynchronous
schedule. An isochronous transfer descriptor (iTD or siTD) in the asynchronous schedule yields undefined
results.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Universal Serial Bus Interface
Figure 16-44.
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