Freescale Semiconductor MPC8313E Family Reference Manual page 415

Table 9-11 describes the TIMING_CFG_2 fields.
Bits Name
0 —
1–3 ADD_LAT
1
4–8 CPO
9 —
10–12 WR_LAT
13–15 —
16–18 RD_TO_PRE
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Table 9-11. TIMING_CFG_2 Field Descriptions
Reserved
Additive latency. The additive latency must be set to a value less than TIMING_CFG_1[ACTTORW].
(DDR2-specific)
000 0 clocks
001 1 clock
010 2 clocks
011 3 clocks
100 4 clocks
101 5 clocks
110 Reserved
111 Reserved
MCAS-to-preamble override. Defines the number of DRAM cycles between when a read is issued
and when the corresponding DQS preamble is valid for the memory controller. For these decodings,
"READ_LAT" is equal to the CAS latency plus the additive latency.
00000READ_LAT + 1
00001Reserved
00010READ_LAT
00011READ_LAT + 1/4
00100READ_LAT + 1/2
00101READ_LAT + 3/4
00110READ_LAT + 1
00111 READ_LAT + 5/4
01000READ_LAT + 3/2
01001READ_LAT + 7/4
01010READ_LAT + 2
01011READ_LAT + 9/4
Reserved
Write latency. Note that the total write latency for DDR2 is equal to WR_LAT + ADD_LAT; the write
latency for DDR1 is 1.
000 Reserved
001 1 clock
010 2 clocks
011 3 clocks
100 4 clocks
101 5 clocks
110 6 clocks
111 7 clocks
Reserved
Read to precharge (t ). For DDR2, with a non-zero ADD_LAT value, takes a minimum of
RTP
ADD_LAT + t cycles between read and precharge. For DDR1 with burst length of 4, must be set
RTP
to 010; for DDR1 with burst length of 8, must be set to 100.
000 Reserved
001 1 cycle
010 2 cycles
011 3 cycles
Description
01100 READ_LAT + 5/2
01101 READ_LAT + 11/4
01110 READ_LAT + 3
01111 READ_LAT + 13/4
10000READ_LAT + 7/2
10001READ_LAT + 15/4
10010READ_LAT + 4
10011 READ_LAT + 17/4
10100READ_LAT + 9/2
10101READ_LAT + 19/4
10110–11111 Reserved
100 4 cycles
101–111 Reserved
DDR Memory Controller
9-17