Master Control Register (Mcr); Snooping By Caches - Freescale Semiconductor MPC8313E Family Reference Manual

Security Engine (SEC) 2.2
14.6.4.7

Master Control Register (MCR)

The master control register (MCR), shown in
provides a means for software to reset the SEC.
0
Field
Reset
R/W
Addr
32
Field
Reset
R/W
Addr
Table 14-40 describes the MCR fields.
Bits Names
0–21 — Reserved
22–23 Priority Priority on master bus. The setting of these bits determines the transaction priority level the SEC asserts
to the device internal arbiter. The SEC does not dynamically alter its priority level based on system
congestion or SEC utilization, however software may change the SEC priority level in realtime.
00 Lowest priority (default)
01 Next lowest priority
10 Next highest priority
11 Highest priority
24–29 — Reserved
30 GIH Global inhibit. Writing 1 to this bit prevents output IPM_SNOOP from being asserted.
0 Permit assertion of IPM_SNOOP, allowing the system cache to snoop bus transactions initiated by the
SEC.
1 Prevent assertion of IPM_SNOOP, preventing the system cache from snooping
31 SWR Software reset. Writing 1 to this bit will cause a global software reset. Upon completion of the reset, this
bit will be automatically cleared.
0 Do not reset
1 Global reset
14.6.5

Snooping by Caches

SEC transactions can be snooped by the MPC8313E cache if defined as global. This definition is
programmed in the master control register MCR[GI]. See
more details. Note that SEC transactions are defined as global by default.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
14-74
Figure
—
0x0000_0000
39 40 47
0x0000_0000
Figure 14-47. Master Control Register (MCR)
Table 14-40. MCR Field Descriptions
14-47, controls certain functions in the controller and
21 22
PRIORITY
R/W
0x3_ 1030
48
R/W
0x 3_1034
Description
14.6.4.7, "Master Control Register (MCR),"
23 24 29 30
— GIH SWR
55 56
Freescale Semiconductor
31
63
for