Freescale Semiconductor MPC8313E Family Reference Manual page 402

DDR Memory Controller
Table 9-1. DDR Memory Interface Signal Summary (continued)
Name
MDM[0:3] Data mask
MCK DRAM clock outputs
MCK DRAM clock outputs (complement)
MCKE DRAM clock enable
MODT[0:1] DRAM on-die termination external control.
MDVAL Memory debug data valid
MSRCID[0:4] Memory debug source ID
Table 9-2 shows the memory address signal mappings.
1
Auto-precharge for DDR signaled on A10 when DDR_SDRAM_CFG[PCHB8] = 0.
2
Auto-precharge for DDR signaled on A8 when DDR_SDRAM_CFG[PCHB8] = 1.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
9-4
Function/Description
Table 9-2. Memory Address Signal Mappings
Signal Name (Outputs)
msb MA14
MA13
MA12
MA11
MA10
MA9
MA8
MA7
MA6
MA5
MA4
MA3
MA2
MA1
lsb MA0
msb MBA2
MBA1
lsb MBA0
JEDEC DDR DIMM Signals (Inputs)
A14
A13
A12
A11
A10 (AP for DDR)
A9
A8 (alternate AP for DDR)
A7
A6
A5
A4
A3
A2
A1
A0
MBA2
MBA1
MBA0
Reset Pins
All zeros 4
Zero 1
One 1
Zero 1
All zeros 2
Zero 1
All zeros 5
1
2
Freescale Semiconductor
I/O
O
O
O
O
O
O
O