Priority Control Register (Pri_Ctrl)—Non-Ehci - Freescale Semiconductor MPC8313E Family Reference Manual

aging counter is less than the AGE_CNT_THRESH value, priority state zero is selected. If the aging
counter is greater than or equal to the AGE_CNT_THRESH value, priority state one is selected.
The two priority states of the aging counter function each have corresponding register bits which are
programmed by the CPU. Thus, when the aging counter function is at priority state zero,
PRI_CTRL[30–31] are selected and used to drive bus priority levels. When the aging counter function is
at priority state one, PRI_CTRL[28–29] are selected and used to drive the priority.
Figure 16-31 shows the age count threshold register.
Offset 0x408
0
R
W
Reset
Table 16-34 describes the age count threshold register fields.
Bits Name
0–17 — Reserved, should be cleared
18–31 Threshold Aging counter threshold value.
The setting of AGE_CNT_THRESH is highly dependent on both the mix of other controllers operating on
the system bus as well as the kind of traffic moving through the USB controller. A recommended approach
is first to try leaving the aging mechanism disabled and see if the USB meets performance requirements.
If USB performance does not meet application requirements, try the following settings:
• Set PRI_CTRL[pri_lvl0] to 0.
• Set tPRI_CTRL[pri_lvl1] to 3.
• Set AGE_CNT_THRESH to 40.
This combination works for a wide variety of applications. If this combination still does not meet
application requirements, try lowering AGE_CNT_THRESH by 5. On the contrary, the setting 40 may be
too conservative for some applications. If USB performance is acceptable at 40, try raising the value in
increments of 5. Raising AGE_CNT_THRESH benefits the other controllers on the system bus by
reducing the frequency that this USB controller raises its priority to the arbiter.
16.3.2.26 Priority Control Register (PRI_CTRL)—Non-EHCI
Note that this register uses big-endian byte ordering and is not defined in the EHCI specification. The
priority control (PRI_CTRL) register sets the priority level for each of two priority states. The priority state
is determined by the value programmed in the AGE_CNT_THRESH register and the number of csb_clk
cycles that a particular transaction takes to complete.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
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Figure 16-31. Age Count Threshold (AGE_CNT_THRESH)
Table 16-34. AGE_CNT_THRESH Register Field Descriptions
17 18
All zeros
Description
Universal Serial Bus Interface
Access: Read/Write
Threshold
16-43
31