Chip-Select Assertion Timing - Freescale Semiconductor MPC8313E Family Reference Manual

Powerquicc ii pro integrated processor

Hide thumbs Also See for MPC8313E:

Table of Contents

Enhanced Local Bus Controller

Option Register Attributes

Times in parentheses are specific for the case LCRR[CLKDIV] = 2; other times apply to all CLKDIV values.

Chip-Select Assertion Timing

The banks selected to work with the GPCM support an option to drive the LCSn signal with different

timings (with respect to the external address/data bus). LCSn can be driven in any of the following ways:

Simultaneous with the latched memory address. (This refers to the externally latched address and

not the address timing on LAD. That is, the chip select does not assert during LALE).

One quarter of a clock cycle later (for LCRR[CLKDIV] = 4, 8).

One half of a clock cycle later (for LCRR[CLKDIV] = 2, 4, or 8).

One clock cycle later (for LCRR[CLKDIV] = 4), when ORn[XACS] = 1.

Two clock cycles later (for LCRR[CLKDIV] = 2, 4, or 8), when ORn[XACS] = 1.

Three clock cycles later (for LCRR[CLKDIV] = 2, 4, or 8), when ORn[XACS] = 1 and

ORn[TRLX] = 1.

MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3

Table 10-33. GPCM Write Control Signal Timing (continued)

Signal Timing (LCLK clock cycles)

1¾ + 2 × SCY

1½ + 2 × SCY

1½ + 2 × SCY

1¼ + 2 × SCY

2¾ + 2 × SCY

2¾ + 2 × SCY

2¾ + 2 × SCY

3¾ + 2 × SCY

Freescale Semiconductor

Table of Contents