Freescale Semiconductor MPC8313E Family Reference Manual page 939

Initialize SerDes to select SGMII. The initialization sequence should be prepended with SerDes initialization.
set source clock divide by 14 for example to insure that MDC clock speed is not less than 2.5 MHz
Set up the MII Mgmt for a read cycle to TBI's Control register (write the PHY address and Register address),
the control register (CR) is at offset address 0x00 from the TBI's address.
Perform an MII Mgmt read cycle to verify state of TBI Control Register (optional)
(Uses the TBI address and Register address placed in MIIMADD register),
Set up the MII Mgmt for a write cycle to TBICON register (write the PHY address and Register address),
Writing to MII Mgmt Control with 16-bit data intended for TBICON register,
This sets TBI in single clock mode and MII Mode off to enable communication with SerDes.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Table 15-177. SGMII Mode Register Initialization Steps
MACCFG1[1000_0000_0000_0000_0000_0000_0000_0000]
Clear Soft_Reset,
MACCFG1[0000_0000_0000_0000_0000_0000_0000_0000]
Initialize MACCFG2,
MACCFG2[0000_0000_0000_0000_0111_0010_0000_0101]
(I/F Mode = 2, Full Duplex = 1)
(Set I/F mode = 1 in SGMII 10/100 Mbps speed)
Initialize ECNTRL,
ECNTRL[0000_0000_0000_0000_0001_0000_0010_0010]
(This example has Statistics Enable = 1, TBIM = 1, SGMIIM = 1)
(Set R100M = 1 in SGMII 100 Mbps speed)
Initialize MAC Station Address
MACSTNADDR2[0110_0000_0000_0010_0000_0000_0000_0000]
to 02608C:876543, for example.
Initialize MAC Station Address
MACSTNADDR1[0100_0011_0110_0101_1000_0111_1000_1100]
to 02608C:876543, for example.
Assign a Physical address to the TBI,
TBIPA[0000_0000_0000_0000_0000_0000_0001_0000]
set to 16, for example.
Setup the MII Mgmt clock speed,
MIIMCFG[0000_0000_0000_0000_000_0000_0000_0101]
Read MII Mgmt Indicator register and check for Busy = 0,
MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000]
This indicates that the eTSEC MII Mgmt bus is idle.
MIIMADD[0000_0000_0000_0000_0001_0000_0000_0000]
Clear MIIMCOM[Read Cycle]
Set MIIMCOM[Read Cycle]
When MIIMIND[BUSY] = 0,
read the MIIMSTAT and look for AN Enable and other bit information.
MIIMADD[0000_0000_0000_0000_0001_0000_0001_0001]
The TBICON register is at offset address 0x11 from the TBI's address.
Perform an MII Mgmt write cycle to TBI.
MIIMCON[0000_0000_0000_0000_0000_0000_0010_0000]
Set Soft_Reset,
Enhanced Three-Speed Ethernet Controllers
15-209