Split Transaction Scheduling Mechanisms For Isochronous - Freescale Semiconductor MPC8313E Family Reference Manual

Universal Serial Bus Interface
a single isochronous scheduling model and adds the additional feature that all data received from the
endpoint (per split transaction) must land into a contiguous buffer.

16.6.12.3.1 Split Transaction Scheduling Mechanisms for Isochronous

Full-speed isochronous transactions are managed through a transaction translator's periodic pipeline. As
with full- and low-speed interrupt, system software manages each transaction translator's periodic pipeline
by budgeting and scheduling exactly during which microframes the start-splits and complete-splits for
each full-speed isochronous endpoint occur. The requirements described in Section 16.6.12.2.1, "Split
Transaction Scheduling Mechanisms for Interrupt," apply.
Figure 16-57 illustrates the general scheduling boundary conditions that are supported by the EHCI
periodic schedule. The S and C labels indicate microframes where software can schedule start- and
n n
complete-splits (respectively). The H-Frame boundaries are marked with a large, solid bold vertical line.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor 16-107