Endpoint Status Register (Endptstatus)—Non-Ehci - Freescale Semiconductor MPC8313E Family Reference Manual

Table 16-28 describes the endpoint flush register fields.
Bits Name
31–19 — Reserved, should be cleared.
18–16 FETB Flush endpoint transmit buffer. Writing a one to a bit(s) in this register will cause the associated endpoint(s) to
clear any primed buffers. If a packet is in progress for one of the associated endpoints, then that transfer will
continue until completion. Hardware will clear this register after the endpoint flush operation is successful.
FETB[2] (bit 18 of the register) corresponds to endpoint 2.
15–3 — Reserved, should be cleared.
2–0 FERB Flush endpoint receive buffer. Writing a one to a bit(s) will cause the associated endpoint(s) to clear any primed
buffers. If a packet is in progress for one of the associated endpoints, then that transfer will continue until
completion. Hardware will clear this register after the endpoint flush operation is successful. FERB[2]
corresponds to endpoint 2.
16.3.2.20 Endpoint Status Register (ENDPTSTATUS)—Non-EHCI
The endpoint status register, shown in
is only used in device mode.
Offset 0x1B8
31
R
W
Reset
Table 16-29 describes the endpoint status fields.
Bits Name
31–19 — Reserved, should be cleared
18–16 ETBR Endpoint transmit buffer ready. One bit for each endpoint indicates status of the respective endpoint buffer. This
bit is set by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME
register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint
indicating ready. This delay time varies based upon the current USB traffic and the number of bits set in the
ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the
ENDPTFLUSH register. ETBR[2] (bit 18 of the register) corresponds to endpoint 2.
Note that these bits are momentarily cleared by hardware during hardware endpoint re-priming operations
when a dTD is retired, and the dQH is updated.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Table 16-28. ENDPTFLUSH Register Field Descriptions
Figure 16-25, is not defined in the EHCI specification. This register
21 18
ETBR
—
Figure 16-26. Endpoint Status (ENDPTSTATUS)
Table 16-29. ENDPTSTATUS Register Field Descriptions
Description
16 15
All zeros
Description
Universal Serial Bus Interface
Access: Read only
3
—
2 0
ERBR
16-37