Cache Units; Bus Interface Unit (Biu) - Freescale Semiconductor MPC8313E Family Reference Manual

e300 Processor Core Overview
See Section 7.3.5.2, "Implementation-Specific Memory Management," for more information about
memory management for the core.
7.1.5.2

Cache Units

The e300c3 provides 16-Kbyte, four-way set-associative instruction and data caches. The cache block is
32 bytes long. The caches adhere to a write-back policy, but the e300 core allows control of cacheability,
write policy, and memory coherency at the page and block levels. The caches use a pseudo LRU
replacement policy.
As shown in Figure 7-1the caches provide a 64-bit interface to the instruction fetch unit and LSU. The
surrounding logic selects, organizes, and forwards the requested information to the requesting unit. Write
operations to the cache can be performed on a byte basis, and a complete read-modify-write operation to
the cache can occur in each cycle.
The load/store and instruction fetch units provide the caches with the address of the data or instruction to
be fetched. In the case of a cache hit, the cache returns two words to the requesting unit.
Because the data cache tags are single-ported, simultaneous load/store and snoop accesses cause resource
contention. Snoop accesses have the highest priority and are given first access to the tags, unless the snoop
access coincides with a tag write; in this case the snoop is retried and must rearbitrate for cache access.
Loads or stores deferred due to snoop accesses are performed on the clock cycle following the snoop.
The e300 core includes a new instruction cancel extension. The instruction cancel extension improves
utilization of the instruction cache during cancel operations. It allows a new instruction fetch to be issued
to the cache or to the bus if a canceled instruction fetch is pending or active on the bus. This supports
hit-under-cancel and miss-under-cancel instruction fetch operations.
7.1.6

Bus Interface Unit (BIU)

Because the caches are on-chip, write-back caches, the most common transactions are burst-read memory
operations, burst-write memory operations, and single-beat (noncacheable or write-through) memory read
and write operations. There can also be address-only operations, variants of the burst and single-beat
operations, (for example, global memory operations that are snooped and atomic memory operations), and
address retry activity (for example, when a snooped read access hits a modified cache block).
Memory accesses can occur in single-beat (1–8 bytes) and four-beat burst (32 bytes) data transfers on the
64-bit data bus. The address and data buses operate independently to support pipelining and split
transactions during memory accesses.
The e300 bus interface unit (BIU) has been enhanced to allow a pipeline slot to become available once a
previous transaction has been granted the data bus (that is, as early as when the data tenure starts rather
than after the data tenure completes), thus allowing for greater bus utilization in systems that support it.
This is sometimes referred to as 1 1/2-level pipelining.
Typically, memory accesses are weakly ordered, meaning that sequences of operations, including
load/store string and multiple instructions, do not necessarily complete in the order they begin. This weak
ordering maximizes the efficiency of the bus without sacrificing coherency of the data. The core allows
read operations to precede store operations (except when a dependency exists, or in cases where a
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