Instruction And Data Cache Way-Locking; Interrupt Model; Powerpc Interrupt Model - Freescale Semiconductor MPC8313E Family Reference Manual

e300 Processor Core Overview
Cache coherency is enforced by on-chip bus snooping logic. Because the e300 core data cache tags are
single-ported, a simultaneous load/store and snoop access represents a resource contention. The snoop
access is given first access to the tags. The load or store then occurs on the clock following the snoop.
Parity is now integrated into both instruction and data cache memory. A machine check interrupt is now
taken upon the detection of an instruction or data cache parity error. Parity is checked whenever valid data
is returned from the instruction or data cache for a cache hit or whenever valid data is read out of the cache
for a castout or snoop-push operation.
7.3.3.3

Instruction and Data Cache Way-Locking

The e300 core implements instruction and data cache way-locking, which guarantees that certain memory
accesses will hit in the cache. This provides deterministic access times for those accesses.
7.3.4

Interrupt Model

This section describes the PowerPC interrupt model and the e300 core implementation specifically.
7.3.4.1

PowerPC Interrupt Model

The PowerPC interrupt mechanism allows the core to change to supervisor state as a result of external
signals, errors, or unusual conditions arising in the execution of instructions. The conditions that can cause
interrupts are called exceptions. When interrupts occur, information about the state of the core is saved to
certain registers and the core begins execution at an address (interrupt vector) predetermined for each
interrupt type. Interrupts are processed in supervisor mode.
Some interrupts, such as program interrupts, can be triggered by a broad range of exception conditions.
Other interrupts, such as the decrementer interrupt, have only a single exception condition. Although
multiple exception conditions can map to a single interrupt vector, a more specific condition may be
determined by examining a register associated with the interrupt—for example, the DSISR and the
FPSCR. Additionally, some exception conditions can be explicitly enabled or disabled by software.
The PowerPC architecture requires that interrupts be handled in program order; therefore, although a
particular implementation may recognize exception conditions out of order, they are presented strictly in
order. When an instruction-caused interrupt is recognized, any unexecuted instructions that appear earlier
in the instruction stream, including any that have not yet entered the execute stage, are required to complete
before the interrupt is taken. Any interrupts caused by those instructions are handled first. Likewise,
asynchronous, precise interrupts are recognized when they occur, but are not handled until the instruction
currently in the completion stage successfully completes execution or generates an interrupt, and the
completed store queue is emptied.
Unless a catastrophic condition causes a system reset or machine check interrupt, only one interrupt is
handled at a time. If, for example, a single instruction encounters multiple interrupt conditions, those
conditions are handled sequentially. After the interrupt handler completes, the instruction execution
continues until the next interrupt condition is encountered. However, in many cases there is no attempt to
re-execute the instruction. This method of recognizing and handling interrupts sequentially guarantees that
interrupts are recoverable.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
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