Freescale Semiconductor MPC8313E Family Reference Manual page 120

Memory Map
Offset
0x0_507C– Reserved
0x0_5080
0x0_5084 MRTPR—Memory refresh timer prescaler register
0x0_5088 MDR—UPM/FCM data register
0x0_508C Reserved
0x0_5090 LSOR—Special operation initiation register
0x0_5094– Reserved
0x0_509C
0x0_50A0 LURT—UPM refresh timer
0x0_50A4– Reserved
0x0_50AC
0x0_50B0 LTESR—Transfer error status register
0x0_50B4 LTEDR—Transfer error check disable register
0x0_50B8 LTEIR—Transfer error interrupt enable register
0x0_50BC LTEATR—Transfer error attributes register
0x0_50C0 LTEAR—Transfer error address register
0x0_50C4– Reserved
0x0_50CC
0x0_50D0 LBCR—Local bus configuration register
0x0_50D4 LCRR—Clock ratio register
0x0_50D8– Reserved
0x0_50DC
0x0_50E0 FMR–Flash mode register
Note: FMR[BOOT] is set during reset if BR0[MSEL] selects
FCM as the boot controller.
0x0_50E4 FIR–Flash instruction register
0x0_50E8 FCR–Flash command register
0x0_50EC FBAR–Flash block address register
0x0_50F0 FPAR–Flash page address register
0x0_50F4 FBCR–Flash byte count register
0x0_50F8–0 Reserved
x0_5FFC
0x0_6000– Reserved, should be cleared
0x0_6FFF
0x0_7000–
Reserved, should be cleared
0x0_701F
0x0_7020 SPMODE—SPI mode register
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
2-14
Table 2-2. Memory Map (continued)
Register
Serial Peripheral Interface (SPI)
Access Reset
— —
R/W 0x0000_0000
R/W 0x0000_0000
— —
R/W 0x0000_0000
— —
R/W 0x0000_0000
— —
Read/ 0x0000_0000
bit-reset
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
— —
R/W 0x0004_0000
R/W 0x8000_0008
— —
R/W 0x0000_0800
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
— —
— —
— —
R/W 0x0000_0000
Freescale Semiconductor
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