Freescale Semiconductor MPC8313E Family Reference Manual page 34

Paragraph
Number
16.9.6.1.2
16.10 Timing Diagrams ....................................................................................................... 16-159
2
17.1 I C Introduction ............................................................................................................. 17-1
2
17.1.1 I C Features ............................................................................................................... 17-2
2
17.1.2 I C Modes of Operation............................................................................................. 17-2
2
17.2 I C External Signal Descriptions................................................................................... 17-3
2
17.2.1 I C Signal Overview.................................................................................................. 17-3
2
17.2.2 I C Detailed Signal Descriptions............................................................................... 17-3
2
17.3 I C Memory Map/Register Definition........................................................................... 17-4
2
17.3.1 I C Register Descriptions .......................................................................................... 17-5
2
17.3.1.1 I Cn Address Register (I2CnADR) ....................................................................... 17-5
2
17.3.1.2 I Cn Frequency Divider Register (I2CnFDR)....................................................... 17-6
2
17.3.1.3 I Cn Control Register (I2CnCR) ........................................................................... 17-7
2
17.3.1.4 I Cn Status Register (I2CnSR) .............................................................................. 17-8
2
17.3.1.5 I Cn Data Register (I2CnDR)................................................................................ 17-9
17.3.1.6 Digital Filter Sampling Rate Register (I2CnDFSRR) ........................................... 17-9
17.4 Functional Description................................................................................................. 17-10
17.4.1 Transaction Protocol ................................................................................................ 17-10
17.4.1.1 START Condition ................................................................................................ 17-11
17.4.1.2 Slave Address Transmission ................................................................................ 17-11
17.4.1.3 Repeated START Condition ................................................................................ 17-12
17.4.1.4 STOP Condition................................................................................................... 17-12
17.4.1.5 Protocol Implementation Details ......................................................................... 17-12
17.4.1.5.1
17.4.1.5.2
17.4.1.6 Address Compare-Implementation Details ....................................................... 17-13
17.4.2 Arbitration Procedure .............................................................................................. 17-13
17.4.2.1 Arbitration Control .............................................................................................. 17-14
17.4.3 Handshaking ............................................................................................................ 17-14
17.4.4 Clock Control........................................................................................................... 17-14
17.4.4.1 Clock Synchronization......................................................................................... 17-15
17.4.4.2 Input Synchronization and Digital Filter ............................................................. 17-15
17.4.4.2.1
17.4.4.2.2
17.4.4.3 Clock Stretching .................................................................................................. 17-15
17.4.5 Boot Sequencer Mode.............................................................................................. 17-15
17.4.5.1 Using the Boot Sequencer for Reset Configuration ............................................ 17-16
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
xxxiv
Contents
Port Speed Detection ..................................................................................... 16-158
I
Transaction Monitoring-Implementation Details.......................................... 17-12
Control Transfer-Implementation Details ..................................................... 17-12
Input Signal Synchronization .......................................................................... 17-15
Filtering of SCLn and SDAn Lines ................................................................. 17-15
Title
Chapter 17
2
C Interfaces
Page
Number
Freescale Semiconductor