Freescale Semiconductor MPC8313E Family Reference Manual page 307

Table 6-2 describes ACR fields.
Bits Name
0–6 — Write reserved, read = 0
7 COREDIS Core disable. Specifies whether CPU is disabled. When CPU is disabled, it cannot be granted on the
bus by the arbiter. After reset, this bit receives its value from the reset configuration bit of COREDIS
and can be configured by software. Also, if boot source is boot sequencer, COREDIS must be set to
1 at reset and the last transaction of the boot sequencer must set COREDIS to 0, if CPU enable is
needed.
0 CPU enabled.
1 CPU disabled.
8–9 — Write reserved, read = 0
10–11 — Reserved. Write should preserve reset value.The reset value is a function of the core PLL
configuration, which is part of the reset configuration word. When the core is set to operate at 1:1 or
3:2 bus clock, these bits are set to '01' during reset; otherwise, they are set to '00'.
12 — Write reserved, read = 0
13–15 PIPE_DEP Pipeline depth (number of outstanding transactions).
000 Pipeline depth 1 (1 outstanding transaction)
001 Pipeline depth 2 (2 outstanding transactions)
010 Pipeline depth 3 (3 outstanding transactions)
011 Pipeline depth 4 (4 outstanding transactions)
1xx Reserved
16 — Write reserved, read = 0
17–19 PCI_RPTCNT PCI repeat count.
Specifies the maximum number of consecutive transactions, that PCI master can perform, using
REPEAT request mode.
000 One consecutive transaction (REPEAT request mode disable)
001 Two consecutive transactions
010 Three consecutive transactions
011 Four consecutive transactions
100 Five consecutive transactions
101 Six consecutive transactions
110 Seven consecutive transactions
111 Eight consecutive transactions
20 — Write reserved, read = 0
21–23 RPTCNT Repeat count. Specifies the maximum number of consecutive transactions, that any master (except
PCI) can perform, using REPEAT request mode.
000 1 consecutive transactions (REPEAT request mode disable)
001 2 consecutive transactions
010 3 consecutive transactions
011 4 consecutive transactions
100 5 consecutive transactions
101 6 consecutive transactions
110 7 consecutive transactions
111 8 consecutive transactions
Note: It is recommended not to program this field for more than four consecutive transactions.
24–25 — Write reserved, read = 0
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Table 6-2. ACR Field Descriptions
Description
Arbiter and Bus Monitor
6-3