System Error Status Register (Sersr) - Freescale Semiconductor MPC8313E Family Reference Manual

Integrated Programmable Interrupt Controller (IPIC)
Table 8-20 defines the bit fields of SECNR.
Bits Name
MIXB0T MIXB0 priority position IPIC output interrupt type. Defines which type of the IPIC output interrupt signal ( int ,
0–1
cint , or smi ) asserts its request to the core in the MIXB0 priority position. These bits can be changed
dynamically. The definition of MIXB0T is as follows:
00 int request is asserted to the core for MIXB0.
01 smi request is asserted to the core for MIXB0.
10 cint request is asserted to the core for MIXB0.
11 Reserved
2–3 MIXB1T Same as MIXB0T, but for MIXB1T.
4–7 — Write ignored, read = 0
8–9 MIXA0T MIXA0 priority position IPIC output interrupt Type. Defines which type of the IPIC output interrupt signal ( int ,
cint , or smi ) asserts its request to the core in the MIXA0 priority position. These bits can be changed
dynamically. The definition of MIXA0T is as follows:
00 int request is asserted to the core for MIXA0.
01 smi request is asserted to the core for MIXA0.
10 cint request is asserted to the core for MIXA0.
11 Reserved
10–11 MIXA1T Same as MIXA0T, but for MIXA1T.
12–15 — Write ignored, read = 0
Each bit defines the edge detect mode for the external IRQ n interrupt signals, determines whether the
16–23 EDIx
corresponding IRQ n signal asserts an interrupt request upon either a high-to-low change or low assertion
on the pin. The corresponding IRQ n signal asserts an interrupt request as follows:
0 Low assertion on IRQ n generates an interrupt request (level sensitive).
1 High-to-low change on IRQ n generates an interrupt request (edge sensitive).
24–31 — Write ignored, read = 0
8.5.13

System Error Status Register (SERSR)

The bits in the SERSR, shown in
source machine check (mcp) conditions listed in
interrupt controller sets the corresponding SERSR bit.
Offset 0x40
0
R
W
Reset
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
8-22
Table 8-20. SECNR Field Descriptions
Figure 8-16, correspond to the external and internal non-maskable error
Table
INT n (Implemented bits are listed in
Figure 8-16. System Error Status Register (SERSR)
Description
8-21. When an error interrupt signal is received, the
Table 8-21)
All zeros
Access: Read/write
31
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