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System initialization data is optionally loaded from I
hardware
1.2.10
DMA Controller
The DMA engine is capable of transferring blocks of data from any legal address range to any other legal
address range. Therefore, it can perform a DMA transfer between any of its I/O or memory ports, or even
between two devices or locations on the same port.
The DMA controller offers the following features:
•
Four high-speed/high-bandwidth channels accessible by local and remote masters
•
Basic DMA operation modes (direct, simple chaining)
•
Support for misaligned transfers
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Programmable bandwidth control between channels
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Interrupt on error and completed segment or chain
1.2.11
Dual Universal Asynchronous Receiver/Transmitter (DUART)
The device includes a DUART intended for use in maintenance, bring up, and debug systems. The device
provides a standard four-wire handshake (TXD, RXD, RTS, CTS) for each port. The DUART is a slave
interface. An interrupt is provided to the interrupt controller or optionally steered externally to allow
device handshakes. Interrupts are generated for transmit, receive, and line status.
The DUART supports full-duplex operation. It is compatible with the PC16450 and PC16550
programming models. The transmitter and receiver both support 16-byte FIFOs.
Software programmable baud rate generators divide the system clock to generate a 16x clock. Serial
interface data formats (data length, parity, 1/1.5/2 STOP bit, baud rate) are also software selectable.
The DUART includes the following features:
•
Full-duplex operation
•
Programming model compatible with the original PC16450 UART and the PC16550D (an
improved version of the PC16450 that also operates in FIFO mode)
•
PC16450 register reset values
•
FIFO mode for both transmitter and receiver, providing 16-byte FIFOs
•
Serial data encapsulation and decapsulation with standard asynchronous communication bits
(START, STOP, and parity)
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Maskable transmit, receive, and line status interrupts
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Software-programmable baud rate generators that divide the system clock by 1 to (2
generate a 16x clock for the transmitter and receiver engines
•
Clear to send (CTS) and ready to send (RTS) MODEM control functions
•
Software-selectable serial-interface data format (data length, parity, 1/1.5/2 STOP bit, baud rate)
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Line status registers
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Line-break detection and generation
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
2
C EPROM by boot sequencer embedded
Overview
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