Soft Reset Flow; Reset Configuration; Reset Configuration Signals - Freescale Semiconductor MPC8313E Family Reference Manual

Figure 4-2 shows a timing diagram of the hard reset flow.
CLKIN (Host Mode) or
PCI_CLK/PCI_SYNC_IN
(Agent Mode)
PORESET
(Input)
HRESET
(Input or Output)
TRST
(Input)

Reset Configuration

Input Signals
Reset Configuration
Words Loading
4.2.4

Soft Reset Flow

The SRESET signal can be initiated externally by asserting SRESET. SRESET assertion asserts the sreset
input to the e300 core. No other hardware is reset.
4.3 Reset Configuration
The device is initialized using two complementary methods, latching CFG_RESET_SOURCE and
loading the reset configuration words. Initially, a few input signals are sampled during the assertion of the
PORESET signal. These signals determine whether a reset configuration word is required and the device
source interface from which it is loaded. According to the value on these signals, the device continues
loading the reset configuration word.
4.3.1

Reset Configuration Signals

Reset configuration input signals are on device pins that have other functions when the device is not in
reset state. These input signals are sampled into registers during the assertion of PORESET, after a stable
clock is supplied (PCI_CLK), and must be pulled high or low by external resistors as long as HRESET is
asserted. While the PORESET and HRESET signals are asserted, all other signal drivers connected to
these signals must be in the high-impedance state. Refer to the hardware specifications for proper resistor
values for pulling reset configuration signals high or low.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Stable clock
Start loading reset
configuration words
Figure 4-2. Hard Reset Flow
Reset, Clocking, and Initialization
End loading reset
configuration words.
Duration depends on
source
4-9