Transmit Data Buffer Pointer High Register (Tbdbph); Transmit Buffer Descriptor Pointers 0–7 (Tbptr0–Tbptr) - Freescale Semiconductor MPC8313E Family Reference Manual

Enhanced Three-Speed Ethernet Controllers
Table 15-22 describes the fields of the TR47WT register.
Bits Name
0–7 WT4 Weighting value for TxBD ring 4 when TCTRL[TXSCHED] = 10. On each round of the Tx scheduler, a
minimum of WT4 × 64 bytes of data are scheduled for transmission from TxBD ring 4. Clearing this field
prevents transmission.
8–15 WT5 Weighting value for TxBD ring 5 when TCTRL[TXSCHED] = 10. On each round of the Tx scheduler, a
minimum of WT5 × 64 bytes of data are scheduled for transmission from TxBD ring 5. Clearing this field
prevents transmission.
16–23 WT6 Weighting value for TxBD ring 6 when TCTRL[TXSCHED] = 10. On each round of the Tx scheduler, a
minimum of WT6 × 64 bytes of data are scheduled for transmission from TxBD ring 6. Clearing this field
prevents transmission.
24–31 WT7 Weighting value for TxBD ring 7 when TCTRL[TXSCHED] = 10. On each round of the Tx scheduler, a
minimum of WT7 × 64 bytes of data are scheduled for transmission from TxBD ring 7. Clearing this field
prevents transmission.
15.5.3.2.8

Transmit Data Buffer Pointer High Register (TBDBPH)

The TBDBPH register is written by the user with the most significant address bits common to all TxBD
buffer addresses, TxBD[Data Buffer Pointer]. As a consequence, all Tx buffers must be placed in a 4
gigabyte segment of memory whose base address is prefixed by the bits in TBDBPH. The TxBD ring itself
can reside in a different memory region (based at TBASEH).
TBDBPH register.
Offset eTSEC1:0x2_4180; eTSEC2:0x2_5180
0
R
W
Reset
Table 15-23 describes the fields of the TBDBPH register.
Bits Name
0–27 — Reserved
28–31 TBDBPH Most significant bits common to all data buffer addresses contained in TxBDs. The user must initialize
TBDBPH before enabling the eTSEC transmit function.
15.5.3.2.9 Transmit Buffer Descriptor Pointers 0–7 (TBPTR0–TBPTR7)
TBPTR0–TBPTR7 each contains the low-order 32 bits of the next transmit buffer descriptor address for
their respective TxBD ring.
of their ring's associated TBASE when the TBASE register is written by software. Software must not write
TBPTR0–TBPTR7 while eTSEC is actively transmitting frames. However, TBPTR0– TBPTR7 can be
modified when the transmitter is disabled or when no Tx buffer is in use (after a GRACEFUL STOP
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
15-46
Table 15-22. TR47WT Field Descriptions
Figure 15-18. TBDBPH Register Definition
Table 15-23. TBDBPH Field Descriptions
Figure 15-19 describes the TBPTR registers. These registers takes on the value
Description
Figure 15-18
—
All zeros
Description
describes the definition for the
Access: Read/Write
27 28
TBDBPH
Freescale Semiconductor
31