Master Interface Data Burst Size Register (Burstsize)—Non-Ehci - Freescale Semiconductor MPC8313E Family Reference Manual

Universal Serial Bus Interface
Figure 16-15 shows the endpoint list address register.
Offset 0x158
31
R
W
Reset
Table 16-18 describes the endpoint list address register fields.
Table 16-18. ENDPOINTLISTADDR Register Field Descriptions
Bits Name
31–11 EPBASE Endpoint list address. Address of the top of the endpoint list.
10–0 — Reserved, should be cleared.
16.3.2.10 Master Interface Data Burst Size Register (BURSTSIZE)—Non-EHCI
The master interface data burst size register, shown in
specification. This register is used to control and dynamically change the burst size used during data
movement on the initiator (master) interface.
Offset 0x160
31
R
W
Reset 0 0 0 0 0
Table 16-19 describes the master interface data burst size register fields.
Bits Name
31–16 — Reserved, should be cleared.
15–8 TXPBURST Programable TX burst length. This register represents the maximum length of a burst in 32-bit words
while moving data from system memory to the USB bus. Must not be set to greater that 16.
7–0 RXPBURST Programable RX burst length. This register represents the maximum length of a burst in 32-bit words
while moving data from the USB bus to system memory. Must not be set to greater than 16.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
16-22
EPBASE
Figure 16-15. Endpoint List Address (ENDPOINTLISTADDR)
—
0 0 0 0 0 0 0 0
Figure 16-16. Master Interface Data Burst Size (BURSTSIZE)
Table 16-19. BURSTSIZE Register Field Descriptions
All zeros
Description
Figure 16-16, is not defined in the EHCI
16 15
TXPBURST
0 0 0 0 0 0 1 0
Description
Access: Read/Write
11 10
—
Access: Read/Write
8 7
RXPBURST
0 0 0 0 0 0 1
Freescale Semiconductor
0
0
0 0 0 0