Freescale Semiconductor MPC8313E Family Reference Manual page 787

Figure 15-29 describes the definition for the RQFCR register.
Offset eTSEC1:0x2_4338; eTSEC2:0x2_5338
0 1
R
GPI
W
Reset
Figure 15-29. Receive Queue Filer Table Control Register Definition
Table 15-34 describes the fields of the RQFCR register.
Bit Name
0 GPI General purpose interrupt. When a property matches the value in the RQPROP entry at this index, and
REJ = 0 and AND = 0, the filer will instruct the Rx descriptor controller to set IEVENT[FGPI] when the
corresponding receive frame is written to memory.
If the timer is enabled (TMR_CTRL[TE] = 1), then TMR_PEVENT[RXP] will also be set.
1–15 — Reserved, should be written with zero.
16–21 Q Receive queue index, from 0 to 63, inclusive, written into the Rx frame control block associated with the
received frame. When a property matches the value in the RQPROP entry at this index, and REJ = 0 and
AND = 0, the frame is sent to either RxBD ring 0 (if RCTRL[FSQEN] = 1) or the RxBD ring with index (Q mod
8) and the filing table search is terminated. In the case where RCTRL[FSQEN] = 0, 8 virtual receive queues
are overlaid on every RxBD ring, and software needs to consult the RQ field of the Rx frame control block to
determine which virtual receive queue was chosen.
22 CLE Cluster entry/exit (used in combination with AND bit). This bit brackets clusters, marking the start and end
entries of a cluster. Clusters cannot be nested.
0 Regular RQCTRL entry.
1 If entry matches and AND = 1, treat subsequent entries as belonging to a nested cluster and enter the
cluster; otherwise skip all entries up to and including the next cluster exit. If AND = 0, exit current cluster.
23 REJ Reject frame. This bit and its specified action are ignored if AND = 1.
0 If entry matches, accept frame and file it to RxBD ring Q.
1 If entry matches, reject frame and discard it, ignoring Q.
24 AND AND, in combination with CLE, REJ, and PID match, determines whether the filer will accept or reject a frame,
defer evaluation until the next rule, exit a cluster, or skip a rule or set of rules.
If CLE is zero:
0 Match property[PID] against RQPROP. If matched, accept or reject frame based on REJ. Otherwise skip
to next rule.
1 Match property[PID] against RQPROP. If matched, defer evaluation to next rule. Otherwise, skip all rules
up to and including the next rule with AND = 0. If the next rule with AND = 0 has CLE = 1, then also exit
cluster.
If CLE is one:
0 Match property[PID] against RQPROP. If matched, accept or reject frame based on REJ. Otherwise, exit
cluster.
1 Match property[PID] against RQPROP. If matched, enter cluster. Otherwise, skip all rules up to and
including the next rule while CLE = 1 and AND = 0.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
15 16
—
(undefined)
Table 15-34. RQFCR Field Descriptions
Enhanced Three-Speed Ethernet Controllers
21 22 23
Q CLE REJ AND CMP —
Description
Access: Read/Write
24 25 26 27 28 31
PID
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