Freescale Semiconductor MPC8313E Family Reference Manual page 128

Memory Map
Offset
0x2_438C RBPTR1—RxBD pointer for ring 1
0x2_4390 Reserved
0x2_4394 RBPTR2—RxBD pointer for ring 2
0x2_4398 Reserved
0x2_439C RBPTR3—RxBD pointer for ring 3
0x2_43A0 Reserved
0x2_43A4 RBPTR4—RxBD pointer for ring 4
0x2_43A8 Reserved
0x2_43AC RBPTR5—RxBD pointer for ring 5
0x2_43B0 Reserved
0x2_43B4 RBPTR6—RxBD pointer for ring 6
0x2_43B8 Reserved
0x2_43BC RBPTR7—RxBD pointer for ring 7
0x2_43C0– Reserved
0x2_43FC
0x2_4400 RBASEH–RxBD base address high bits
0x2_4404 RBASE0—RxBD base address of ring 0
0x2_4408 Reserved
0x2_440C RBASE1—RxBD base address of ring 1
0x2_4410 Reserved
0x2_4414 RBASE2—RxBD base address of ring 2
0x2_4418 Reserved
0x2_441C RBASE3—RxBD base address of ring 3
0x2_4420 Reserved
0x2_4424 RBASE4—RxBD base address of ring 4
0x2_4428 Reserved
0x2_442C RBASE5—RxBD base address of ring 5
0x2_4430 Reserved
0x2_4434 RBASE6—RxBD base address of ring 6
0x2_4438 Reserved
0x2_443C RBASE7—RxBD base address of ring 7
0x2_4440–0 Reserved
x2_44BC
0x2_44C0 TMR_RXTS_H*—Rx timer time stamp register high
0x2_44C4 TMR_RXTS_L*—Rx timer time stamp register low
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
2-22
Table 2-2. Memory Map (continued)
Register Access Reset
R/W 0x0000_0000
R 0x0000_0000
R/W 0x0000_0000
R 0x0000_0000
R/W 0x0000_0000
R 0x0000_0000
R/W 0x0000_0000
R 0x0000_0000
R/W 0x0000_0000
R 0x0000_0000
R/W 0x0000_0000
R 0x0000_0000
R/W 0x0000_0000
R 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R 0x0000_0000
R/W 0x0000_0000
R 0x0000_0000
R/W 0x0000_0000
R 0x0000_0000
R/W 0x0000_0000
R 0x0000_0000
R/W 0x0000_0000
R 0x0000_0000
R/W 0x0000_0000
R 0x0000_0000
R/W 0x0000_0000
R 0x0000_0000
R/W 0x0000_0000
R 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
Freescale Semiconductor
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