Freescale Semiconductor MPC8313E Family Reference Manual page 379

Offset 0x28
0 1 2 3
R
SYSD0T SYSD1T
W
Reset
Figure 8-10. System Internal Interrupt Control Register (SICNR)
Table 8-15 defines the bit fields of SICNR.
Bits Name
0–1 SYSD0T SYSD0 priority position IPIC output interrupt type.Defines which type of the IPIC output interrupt signal ( int ,
cint , or smi ) asserts its request to the core in the SYSD0 priority position. These bits cannot be changed
dynamically. (to change it, software must make sure the corresponding interrupt source is masked or it cannot
happen during the change).
The definition of SYSD0T is as follows:
00 int request is asserted to the core for SYSD0.
01 smi request is asserted to the core for SYSD0.
10 cint request is asserted to the core for SYSD0.
11 Reserved
2–3 SYSD1T Same as SYSD0T, but for SYSD1T.
4–23 — Write ignored, read = 0
24–25 SYSA0T SYSA0 priority position IPIC output interrupt type. Defines which type of the IPIC output interrupt signal ( int ,
smi , or cint ) asserts its request to the core in the SYSA0 priority position. These bits can not be changed
dynamically. (If s/w really wants to change it, it must ensure the corresponding interrupt source is masked or
it does not happen during the change).
The definition of SYSA0T is as follows:
00 int request is asserted to the core for SYSA0.
01 smi request is asserted to the core for SYSA0.
10 cint request is asserted to the core for SYSA0.
11 Reserved.
26–27 SYSA1T Same as SYSA0T, but for SYSA1T
28–31 — Write ignored, read = 0
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
4
Table 8-15. SICNR Field Descriptions
Integrated Programmable Interrupt Controller (IPIC)
—
All zeros
Description
Access: Read write
23 24 25 26 27 28
SYSA0T SYSA1T —
31
8-17