Freescale Semiconductor MPC8313E Family Reference Manual page 976

Universal Serial Bus Interface
Bits Name
1 VC VBUS charge. Setting this bit causes the VBus line to be charged. This is used for VBus pulsing during SRP.
0 VD VBUS discharge. Setting this bit causes VBus to discharge through a resistor.
16.3.2.16 USB Mode Register (USBMODE)—Non-EHCI
The USB mode register, shown in
controls the operating mode of the module.
Offset 0x1A8
31
R
W
Reset
Table 16-25 describes the USB mode register fields.
Bits Name
31–5 — Reserved, should be cleared.
4 SDIS Stream disable
In host mode, setting this bit ensures that overruns/underruns of the latency FIFO are eliminated for low
bandwidth systems where the RX and TX buffers are sufficient to contain the entire packet. Enabling stream
disable also has the effect of ensuring the TX latency is filled to capacity or a complete packet is stored in FIFO
before the packet is launched onto the USB.
Note that time duration to pre-fill the FIFO becomes significant when stream disable is active. See
TXFILLTUNING to characterize the adjustments needed for the scheduler when using this feature.
Also note that in systems with high system bus utilization, setting this bit will ensure no overruns or underruns
during operation, at the expense of link utilization. For those who desire optimal link performance, SDIS can be
left clear, and the rules used under the description of the TXFILLTUNING register to limit underruns/overruns.
1 Active.
0 Inactive.
In device mode, setting this bit disables double priming on both RX and TX for low bandwidth systems. This
mode ensures that when the RX and TX buffers are sufficient to contain an entire packet that the standard double
buffering scheme is disabled to prevent overruns/underruns in bandwidth limited systems.
Note that in high-speed mode, all packets received are responded to with a NYET handshake when stream
disable is active.
3 SLOM Setup lockout mode. In device mode, this bit controls behavior of the setup lock mechanism. See
Section 16.8.3.5, "Control Endpoint Operation Model."
1 Setup lockouts off. DCD requires use of setup data buffer tripwire in USBCMD (SUTW).
0 Setup lockouts on
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
16-34
Table 16-24. OTGSC Register Field Descriptions (continued)
Figure 16-22, is not defined in the EHCI specification. This register
—
Figure 16-22. USB Mode (USBMODE)
Table 16-25. USBMODE Register Field Descriptions
Description
All zeros
Description
Access: Read/Write
5 4 3 2 1
SDIS SLOM — CM
Freescale Semiconductor
0