Freescale Semiconductor MPC8313E Family Reference Manual page 598

PCI Bus Interface
Table 13-3. PCI Interface Signals—Detailed Signal Descriptions (continued)
Signal I/O
PCI_AD[31:0] I/O PCI address/data bus. During an address phase, these signals contain a physical address. During a
O
I
PCI_C/BE[3:0] I/O PCI bus command/byte enable.
O
I
PCI_DEVSEL I/O PCI device select.
O
I
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
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data phase, these signals contain the data bytes.
Outputs for the bi-directional PCI address/data bus.
State Asserted/Negated—Represents the physical address during the address phase of a PCI
Meaning transaction. During the data phase(s) of a PCI transaction, the PCI address/data bus
contain the data being written.
PCI_AD[7:0] define the LSB and, PCI_AD[31:24] define the MSB.
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.3
Inputs for the bi-directional PCI address/data bus.
State Asserted/Negated—Represents the address to be decoded as a check for device select
Meaning during the address phase of a PCI transaction or the data being received during the
data phase(s) of a PCI transaction.
PCI_AD[7:0] define the LSB and, PCI_AD[31:24] define the MSB.
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.3
Outputs for the bi-directional command/byte enable.
State Asserted/Negated—During the address phase, PCI_CBE[3:0],define the bus command.
Meaning Byte enables determine which byte lanes carry meaningful data for PCI bus data phases.
The PCI_CBE[0] signal applies to the LSB.
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.3
Inputs for the bi-directional command/byte enable.
State Asserted/Negated—During the address phase, PCI_CBE[3:0], indicate the command that
Meaning another master is sending. During the PCI bus data phase, PCI_CBE[3:0], indicate which
byte lanes are valid.
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.3
Outputs for the bi-directional device select.
State Asserted—The PCI controller has decoded the address and is the target of the current
Meaning access.
Negated—The PCI controller has decoded the address and is not the target of the current
access.
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.3
Inputs for the bi-directional device select.
State Asserted—Some PCI agents (other than this PCI controller) have decoded its address as
Meaning the target of the current access.
Negated—No PCI agent has been selected.
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.3
Description
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