Freescale Semiconductor MPC8313E Family Reference Manual page 118

Memory Map
Offset
0x0_3100 I2C2ADR—I
0x0_3104 I2C2FDR—I
2
0x0_3108 I2C2CR—I
2
0x0_310C I2C2SR—I
2
0x0_3110 I2C2DR—I
0x0_3114 I2C2DFSRR—I
0x0_311C– Reserved, should be cleared
0x0_31FF
0x0_3200– Reserved, should be cleared
0x0_3FFF
0x0_4000– Reserved, should be cleared
0x0_44FF
0x0_4500 URBR—ULCR[DLAB] = 0 UART1 receiver buffer register
0x0_4500 UTHR—ULCR[DLAB] = 0 UART1 transmitter holding
register
0x0_4500 UDLB—ULCR[DLAB] = 1 UART1 divisor least significant
byte register
0x0_4501 UIER—ULCR[DLAB] = 0 UART1 interrupt enable register
0x0_4501 UDMB—ULCR[DLAB] = 1 UART1 divisor most significant
byte register
0x0_4502 UIIR—ULCR[DLAB] = 0 UART1 interrupt ID register
0x0_4502 UFCR—ULCR[DLAB] = 0 UART1 FIFO control register
0x0_4502 UAFR—ULCR[DLAB] = 1 UART1 alternate function
register
0x0_4503 ULCR—ULCR[DLAB] = x UART1 line control register
0x0_4504 UMCR—ULCR[DLAB] = x UART1 MODEM control register
0x0_4505 ULSR—ULCR[DLAB] = x UART1 line status register
0x0_4506 UMSR—ULCR[DLAB] = x UART1 MODEM status register
0x0_4507 USCR—ULCR[DLAB] = x UART1 scratch register
0x0_4508– Reserved, should be cleared
0x0_450F
0x0_4510 UDSR—ULCR[DLAB] = x UART1 DMA status register
0x0_4600 URBR—ULCR[DLAB] = 0 UART2 receiver buffer register
0x0_4600 UTHR—ULCR[DLAB] = 0 UART2 transmitter holding
register
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
2-12
Table 2-2. Memory Map (continued)
Register
2
C2 address register
2
C2 frequency divider register
C2 control register
C2 status register
C2 data register
2
C2 digital filter sampling rate register
Access
2
I C2 Controller
R/W
R/W
R/W
R/W
R/W
R/W
—
—
DUART
—
R
W
R/W
R/W
R/W
R
W
R/W
R/W
R/W
R
R
R/W
—
R
R
W
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