Transmit Status Register (Tstat) - Freescale Semiconductor MPC8313E Family Reference Manual

Powerquicc ii pro integrated processor

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Enhanced Three-Speed Ethernet Controllers

TXSCHED Transmit ring scheduling algorithm. This field determines which scheme the transmit scheduler uses to

arbitrate between the enabled TxBD rings. The scheme chosen also controls how the DMACTRL and

TQUEUE bits are interpreted. Ring polling is supported only by mode 00; the other modes require

software to restart rings with the TSTAT register. TCP/IP offload can be enabled with any scheduling

00 Single polled ring mode. TxBD ring 0 is the only ring serviced, even if other rings are enabled and

01 Priority scheduling mode. Frames from enabled TxBD rings are serviced in ascending ring index

10 Modified weighted round-robin scheduling mode. Each TxBD ring is polled in sequence for frames

Transmit Status Register (TSTAT)

This register is read/write-one-to-clear and is written by the eTSEC to convey DMA status information for

each TxBD ring. The halt bit only has meaning for enabled rings. After processing transmit-related

interrupts, software should use TSTAT to restart transmission from rings that may have been affected by

the interrupt condition. In particular, an error condition that prevents eTSEC from continuing transmission

halts DMA from all rings, including the ring that gave rise to the error.

Offset eTSEC1:0x2_4104; eTSEC2:0x2_5104

MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3

Table 15-16. TCTRL Field Descriptions (continued)

ready. In this scheduler mode, the DMACTRL[WOP] and DMACTRL[TOD] bits control polling and

retry behavior. This mode supports ring polling, and allows fetching of a non-ready TxBD to be retried

that are ready for transmission. If a non-ready TxBD is fetched from a ring, that ring is removed from

the scheduling pool until software re-enables it. Ready frames are repeatedly transmitted from a

chosen ring until its transmission quota is exhausted. The transmission quota for TxBD ring n is set

to WT n × 64 bytes, where WT n is a weight from the TR03WT/TR47WT registers. If a ring transmits

more data than its quota allows, the excess is deducted from its quota on the next transmission

opportunity, thereby preventing large frames from monopolizing the eTSEC bandwidth.

Figure 15-12. TSTAT Register Definition

Figure 15-12

describes the TSTAT

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