Freescale Semiconductor MPC8313E Family Reference Manual page 933

Table 15-172. RMII Mode Register Initialization Steps (continued)
Set up the MII Mgmt for a read cycle to the PHY MII Mgmt register (write the PHY address and Register address),
The PHY Status register is at address 0x1 and in this case the PHY Address is 0x2.
(Uses the PHY address (2) and Register address (1) placed in MIIMADD register)
Other information about the link is also returned. (Extend Status, No pre, Remote Fault, An Ability, Link status, extend Ability)
(Uses the PHY address (0x11) and Register address (6) placed in MIIMADD register)
read the MII Mgmt AN Expansion register and check bits 13 and 14. (NP Able and Page Rx'd)
MII Mgmt AN Expansion ---> [0000_0000_0000_0000_0000_0000_0000_0110]
Perform an MII Mgmt read cycle of AN Link Partner Base Page Ability Register. (Optional)
(Uses the PHY address (0x11) and Register address (5) placed in MIIMADD register)
read the MII Mgmt AN Link Partner Base Page Ability register and check bits 9 and 10. (Half and Full Duplex)
MII Mgmt AN Link Partner Base Page Ability ---> [0000_0000_0000_0000_0000_000x_x110_0000]
Setting up the MII Mgmt for a write cycle to TBI MII Mgmt register (write the TBI's address and Register address),
Writing to MII Mgmt Control with 16-bit data intended for TBI's MII Mgmt control register (TBI control),
(Uses the TBI address and Register address placed in MIIMADD register),
Setting up the MII Mgmt for a read cycle to PHY's MII Mgmt register (write the PHY's address and Register address),
the PHY Status control register is at address 0x2 and lets say the PHY Address is 0x2
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Check to see if PHY has completed Auto-Negotiation.
MIIMADD[0000_0000_0000_0000_0000_0010_0000_0001]
Perform an MII Mgmt read cycle of Status Register.
Clear MIIMCOM[Read Cycle]
Set MIIMCOM[Read Cycle]
When MIIMIND[BUSY]=0,
read the MIIMSTAT register and check bit 10. (AN Done)
MIIMSTAT ---> [0000_0000_0000_0000_0000_0000_0010_0000]
Perform an MII Mgmt read cycle of AN Expansion Register.
Setup MIIMADD[0000_0000_0000_0000_0001_0001_0000_0110]
Clear MIIMCOM[Read Cycle]
Set MIIMCOM[Read Cycle]
When MIIMIND[BUSY]=0,
Setup MIIMADD[0000_0000_0000_0000_0001_0001_0000_0101]
Clear MIIMCOM[Read Cycle]
Set MIIMCOM[Read Cycle]
When MIIMIND[BUSY]=0,
MIIMADD[0000_0000_0000_0000_0001_0000_0000_1011]
the TBI control register is at offset address 0x11 from TBIPA
Perform an MII Mgmt write cycle
MIIMCON[0000_0000_0000_0000_0000_0010_0001_0000]
This configures the TBI control to GMII mode and AN sense
Check to see if MII Mgmt write is complete
Read MII Mgmt Indicator register and check for Busy = 0,
MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000]
This indicate that the write cycle was completed
Perform an MII Mgmt read cycle (0ptional)
Set MIIMCOM[Read Cycle]
read the MIIMSTAT register and verify that
MIIMSTAT ---> [0000_0000_0000_0000_0000_0010_0001_0000]
Check to see if PHY has completed Auto-Negotiation
MIIMADD[0000_0000_0000_0000_0000_0010_0000_0010]
Enhanced Three-Speed Ethernet Controllers
15-203