Freescale Semiconductor MPC8313E Family Reference Manual page 959

Powerquicc ii pro integrated processor

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(USBSTS) still shows interrupt sources even if they are disabled by the USBINTR register, allowing

polling of interrupt events by the software.

Offset 0x148

shows the USBINTR register field descriptions.

Reserved, should be cleared.

ULPI interrupt enable. An event completion to the viewport register sets the USBSTS[ULPII]. If the ULPI

enables ULPIE bit to be set, then the USBINT (USBSTS[UI]) occurs.

Reserved, should be cleared.

Sleep enable. This is a non-EHCI bit. When this bit is a one, and USBSTS[SLI] transitions, the USB DR

controller issues an interrupt. The interrupt is acknowledged by software writing a one to USBSTS[SLI].

Only used in device mode.

SOF received enable. This is a non-EHCI bit. When this bit is a one, and USBSTS[SRI] is a one, the

controller issues an interrupt. The interrupt is acknowledged by software clearing USBSTS[SRI].

USB reset enable. This is a non-EHCI bit. When this bit is a one, USBSTS[URI] is a one, the device

controller issues an interrupt. The interrupt is acknowledged by software clearing USBSTS[URI] bit. Only

used in device mode.

Interrupt on async advance enable. When this bit is a one, and USBSTS[AAI] is a one, the controller issues

an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing

USBSTS[AAI]. Only used in host mode.

System error enable. When this bit is a one, and USBSTS[SEI] is a one, the controller issues an interrupt.

The interrupt is acknowledged by software clearing USBSTS[SEI].

MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3

Freescale Semiconductor

Figure 16-10. USB Interrupt Enable (USBINTR)

Table 16-12. USBINTR Register Field Descriptions

Universal Serial Bus Interface

Access: Read/Write

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