Hard Reset Flow - Freescale Semiconductor MPC8313E Family Reference Manual

Reset, Clocking, and Initialization
Figure 4-1 shows a timing diagram of the power-on reset flow.
CLKIN (Host Mode) or
PCI_CLK/PCI_SYNC_IN
(Agent Mode)
PORESET
(Input)
HRESET
(Output)
TRST
(Input)
Reset Configuration
Input Signals
Reset Configuration
Words Loading
4.2.3

Hard Reset Flow

The HRESET signal is initiated externally by asserting HRESET or internally when the device detects a
reason to generate an internal hard reset sequence. In both cases, the device continues asserting HRESET
throughout the HRESET state. The hard reset sequence time varies according to the configuration source
and SYS_CLK_IN (PCI host mode) or PCI_CLK (PCI agent mode) frequency. The reset configuration
input signals (CFG_RESET_SOURCE and CFG_CLKIN_DIV) are not sampled by hard reset (only by
power-on reset), so the device immediately starts loading the reset configuration words and configures the
device as explained in
sequence completes, the device releases the HRESET and signal and exits the HRESET state. An external
pull-up resistor should negate the signals. After negation is detected, a 16-cycle period is taken before
testing for the presence of an external (hard) reset.
Because the device does not sample the reset configuration input signals
(CFG_RESET_SOURCE, CFG_CLKIN_DIV) during a hard reset flow,
setting a new value on those signals (other than that set during power-on
reset) has no effect.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
4-8
Stable clock
Min. 32
SYS_CLK_IN/PCI_CLK
cycles
Figure 4-1. Power-On Reset Flow
Section 4.3.3, "Loading the Reset Configuration Words."
Start loading reset
configuration words
NOTE
PLLs are
locked (no
external
indication)
End loading reset
configuration words.
Duration depends on
source
After the configuration
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