Freescale Semiconductor MPC8313E Family Reference Manual page 13

Paragraph
Number
9.3.2 Detailed Signal Descriptions ....................................................................................... 9-5
9.3.2.1 Memory Interface Signals........................................................................................ 9-5
9.3.2.2 Clock Interface Signals............................................................................................ 9-7
9.3.2.3 Debug Signals.......................................................................................................... 9-8
9.4 Memory Map/Register Definition ................................................................................... 9-8
9.4.1 Register Descriptions................................................................................................... 9-9
9.4.1.1 Chip Select Memory Bounds (CSn_BNDS)............................................................ 9-9
9.4.1.2 Chip Select Configuration (CSn_CONFIG).......................................................... 9-10
9.4.1.3 DDR SDRAM Timing Configuration 3 (TIMING_CFG_3)................................. 9-11
9.4.1.4 DDR SDRAM Timing Configuration 0 (TIMING_CFG_0)................................. 9-12
9.4.1.5 DDR SDRAM Timing Configuration 1 (TIMING_CFG_1)................................. 9-14
9.4.1.6 DDR SDRAM Timing Configuration 2 (TIMING_CFG_2)................................. 9-16
9.4.1.7 DDR SDRAM Control Configuration (DDR_SDRAM_CFG)............................. 9-18
9.4.1.8 DDR SDRAM Control Configuration 2 (DDR_SDRAM_CFG_2)...................... 9-21
9.4.1.9 DDR SDRAM Mode Configuration (DDR_SDRAM_MODE)............................ 9-22
9.4.1.10 DDR SDRAM Mode 2 Configuration (DDR_SDRAM_MODE_2)..................... 9-23
9.4.1.11 DDR SDRAM Mode Control Register (DDR_SDRAM_MD_CNTL)................. 9-24
9.4.1.12 DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) ................. 9-27
9.4.1.13 DDR SDRAM Data Initialization (DDR_DATA_INIT) ....................................... 9-27
9.4.1.14 DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL) ............................. 9-28
9.4.1.15 DDR Initialization Address (DDR_INIT_ADDR)................................................ 9-28
9.4.1.16 DDR IP Block Revision 1 (DDR_IP_REV1) ....................................................... 9-29
9.4.1.17 DDR IP Block Revision 2 (DDR_IP_REV2)........................................................ 9-29
9.5 Functional Description................................................................................................... 9-30
9.5.1 DDR SDRAM Interface Operation............................................................................ 9-33
9.5.1.1 Supported DDR SDRAM Organizations............................................................... 9-34
9.5.2 DDR SDRAM Address Multiplexing........................................................................ 9-35
9.5.3 JEDEC Standard DDR SDRAM Interface Commands ............................................. 9-40
9.5.4 DDR SDRAM Interface Timing................................................................................ 9-41
9.5.4.1 Clock Distribution ................................................................................................. 9-45
9.5.5 DDR SDRAM Mode-Set Command Timing............................................................. 9-45
9.5.6 DDR SDRAM Registered DIMM Mode ................................................................... 9-46
9.5.7 DDR SDRAM Write Timing Adjustments ................................................................ 9-46
9.5.8 DDR SDRAM Refresh .............................................................................................. 9-47
9.5.8.1 DDR SDRAM Refresh Timing.............................................................................. 9-48
9.5.8.2 DDR SDRAM Refresh and Power-Saving Modes ................................................ 9-48
9.5.8.2.1
9.5.9 DDR Data Beat Ordering........................................................................................... 9-50
9.5.10 Page Mode and Logical Bank Retention ................................................................... 9-51
9.6 Initialization/Application Information ........................................................................... 9-52
9.6.1 Programming Differences between Memory Types .................................................. 9-53
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Contents
Self-Refresh in Sleep Mode............................................................................... 9-50
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