Spi Command Register (Spcom); Spi Transmit Data Hold Register (Spitd) - Freescale Semiconductor MPC8313E Family Reference Manual

Serial Peripheral Interface
19.4.1.4

SPI Command Register (SPCOM)

The SPI command register (SPCOM), shown in
Offset 0x02C
0
R
—
W
Reset
Table 19-7 describes the SPCOM fields.
Bits Name
0–8 — Reserved
9 LST This bit represents the last character. Should be set before the last character is written to the SPITD. This
results in SPIE[LT] being set when the character is fully transmitted and by that gives indication about the
frame being fully transmitted.
0 This character is not the last character of the frame
1 This character is the last character of the frame
10–31 — Reserved
19.4.1.5

SPI Transmit Data Hold Register (SPITD)

SPITD holds the character to be transmitted. The number of bits in each character is specified by
SPMODE[LEN]. Each time SPIE[NF] is set, the core can write another character of data to SPITD, if there
is no error indication in the SPIE. At the end of the frame the core should set SPCOM[LST] and prepare
the last character of data.
Offset 0x030
0
R
W
Reset
Table 19-8 shows the field descriptions of the SPI transmit data hold register.
Bits Name
0–31 DATA These bits are the data to be sent.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
19-14
8 9 10
LST
Figure 19-9. SPI Command Register Definition
Table 19-7. SPCOM Field Descriptions
Figure 19-10 shows the SPI transmit data hold register.
Figure 19-10. SPI Transmit Data Hold Register Definition
Table 19-8. SPI Transmit Data Hold Field Descriptions
Figure 19-9, is used to end SPI operation.
All zeros
Description
DATA
All zeros
Description
Access: Write only
—
Access: Write only
Freescale Semiconductor
31
31