Carry Mask Register 1 (Cam) - Freescale Semiconductor MPC8313E Family Reference Manual

Enhanced Three-Speed Ethernet Controllers
Bits Name
29 C2TNC
30 —
31 C2TDP
15.5.3.6.46 Carry Mask Register 1 (CAM1)
While one of the below mask bits are cleared, the corresponding carry bit in CAR1 is allowed to cause
interrupt indications in register IEVENT[MSR0]. These bits all default to a set state.
describes the definition for the CAM1 register.
Offset eTSEC1:0x2_4738; eTSEC2:0x2_5738
0 1
R
M1 M1
64 127
W
Reset 1 1
16 17
R
M1 M1
RPK RFC
W
Reset 1 1
Figure 15-98. Carry Mask Register 1 (CAM1) Register Definition
Table 15-102 describes the fields of the CAM1 register.
Bits
0
1
2
3
4
5
6
7–13
14
15
16
17
18
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
15-104
Table 15-101. CAR2 Field Descriptions (continued)
Carry register 2 TNCL counter carry bit
Reserved, should be cleared
Carry register 2 TDRP counter carry bit
2 3 4 5
M1 M1 M1 M1
255 511 1K MAX
1 1 1 1
18 19 20 21
M1 M1 M1 M1
RMC RBC RXC RXP
1 1 1 1
Table 15-102. CAM1 Field Descriptions
Name
M164 Mask register 1 TR64 counter carry bit mask
M1127 Mask register 1 TR127 counter carry bit mask
M1255 Mask register 1 TR255 counter carry bit mask
M1511 Mask register 1 TR511 counter carry bit mask
M11k Mask register 1 TR1K counter carry bit mask
M1MAX Mask register 1 TRMAX counter carry bit mask
M1MGV Mask register 1 TRMGV counter carry bit mask
— Reserved
M1REJ Mask register 1 RREJ counter carry bit mask
M1RBY Mask register 1 RBYT counter carry bit mask
M1RPK Mask register 1 RPKT counter carry bit mask
M1RFC Mask register 1 RFCS counter carry bit mask
M1RMC Mask register 1 RMCA counter carry bit mask
Description
6 7
M1
MGV
1 0 0 0
22 23 24 25
M1 M1 M1 M1
RXU RAL RFL RCD
1 1 1 1
Description
Figure 15-98
Access: Read/Write
13
—
0 0 0 0
26 27 28 29
M1 M1 M1 M1
RCS RUN ROV RFR
1 1 1 1
Freescale Semiconductor
14 15
M1 M1
REJ RBY
1 1
30 31
M1 M1
RJB RDR
1 1