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Enhanced Local Bus Controller
accessed bank, the number of bytes to transfer, and the address accessed.
control LBS[0:1].
UPMA
UPMB
UPMC
The uppermost byte select (LBS0), when asserted, indicates that LAD[0:7] contains valid data during a
cycle. Likewise, LBS1 indicates that LAD[8:15] contain valid data. For a UPM refresh timer request, all
LBS[0:1] signals are asserted/negated by the UPM according to the refresh pattern only. Following any
internal bus monitor exception, the LBS[0:1] signals are negated regardless of the exception handling
provided by any UPM exception pattern to prevent spurious writes to external RAM.
10.4.4.4.4
General-Purpose Signals (G n T n , GO n )
The general-purpose signals (LGPL[0:5]) each have two bits in the RAM word that define the logical value
of the signal to be changed at the rising edge of the bus clock and/or at the falling edge of the bus clock.
LGPL0 offers enhancements beyond the other LGPLn lines.
LGPL0 can be controlled by an address line specified in MxMR[G0CL]. To use this feature, G0H and G0L
should be set in the RAM word. For example, for a SIMM with multiple banks, this address line can be
used to switch between internal memory device banks.
10.4.4.4.5
Loop Control (LOOP)
The LOOP bit in the RAM word specifies the beginning and end of a set of UPM RAM words that are to
be repeated. The first time LOOP = 1, the memory controller recognizes it as a loop start word and loads
the memory loop counter with the corresponding contents of the loop field shown in
RAM word for which LOOP = 1 is recognized as a loop end word. When it is reached, the loop counter is
decremented by one.
Continued loop execution depends on the loop counter. If the counter is not zero, the next RAM word
executed is the loop start word. Otherwise, the next RAM word executed is the one after the loop end word.
Loops can be executed sequentially but cannot be nested. Also, special care must be taken:
•
LAST and LOOP must not be set together.
•
Loop start word should not have an AMX change with regard to the previous word.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
10-86
Bank Selected
BR n [MSEL]
BR n [PS]
MUX
Figure 10-66. LBS Signal Selection
Figure 10-66
LA[23:25]
Byte count
Byte-Select
Logic
shows how UPMs
LBS0
LBS1
Table
10-41. The next
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